Abstract
This paper presents how to compute n-bit CRC checksums on FPGAs in parallel. For this task, a specialized logic minimization strategy is outlined. It achieves significantly better results than standard logic optimizers. For n≥96, CRC designs with an n-bit I/O interface are poorly routable. However, for smaller I/O interfaces even a 128-bit CRC can be implemented.
Work partly funded by DFG — SFB 124
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© 1996 Springer-Verlag Berlin Heidelberg
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Braun, M., Friedrich, J., Grün, T., Lembert, J. (1996). Parallel CRC computation in FPGAs. In: Hartenstein, R.W., Glesner, M. (eds) Field-Programmable Logic Smart Applications, New Paradigms and Compilers. FPL 1996. Lecture Notes in Computer Science, vol 1142. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-61730-2_16
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DOI: https://doi.org/10.1007/3-540-61730-2_16
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