Skip to main content

Logic synthesis for FPGAs using a mixed exclusive-/inclusive-OR form

  • Hardware/Software Co-Design
  • Conference paper
  • First Online:
Field-Programmable Logic Smart Applications, New Paradigms and Compilers (FPL 1996)

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 1142))

Included in the following conference series:

  • 174 Accesses

Abstract

Synthesis systems generally represent functions using inclusive-OR sums, although it has often been claimed that using exclusive-OR sums can give significant benefits in some cases. A mixed factored form has been developed which uses both inclusive- and exclusive-OR sums in an attempt to benefit from the properties of both representations. This factored form can be technology dependent, so more exclusive-OR factors will be used if a library with an efficient exclusive-OR implementation is targeted. Techniques for technology mapping AND/EXOR expressions and networks containing both inclusive- and exclusive-OR sums are described. Results show that, for fine-grain FPGAs, the mixed approach generates smaller implementations than either of the forms separately.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Institutional subscriptions

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. D. Brand and T. Sasao. Minimization of AND-EXOR expressions using rewrite rules. IEEE Transactions on Computers, 42(5):568–576, May 1993.

    Google Scholar 

  2. R. Brayton, R. Rudell, A. Sangiovanni-Vincentelli, and A. Wang. MIS: A multiple-level logic optimization system. IEEE Transactions on Computer-Aided Design, CAD-6(6):1062–1081, November 1987.

    Google Scholar 

  3. R. Brayton, R. Rudell, A. Sangiovanni-Vincentelli, and A. Wang. Multilevel logic synthesis. Notes for lectures at Oxford Berkeley Summer Engineering Program, July 1989.

    Google Scholar 

  4. M. Helliwell and M. Perkowski. A fast algorithm to minimize mixed polarity generalized Reed-Muller forms. In Proceedings of the 25th ACM/IEEE Design Automation Conference, pages 427–432. IEEE Computer Society Press, 1988.

    Google Scholar 

  5. Nigel L. K. Lester. Logic Synthesis using Reed-Muller and SOP expressions. PhD thesis, University of Brisol, 1995.

    Google Scholar 

  6. N.L.K. Lester and J. M. Saul. Technology mapping of mixed polarity Reed-Muller representations. In Proceedings of the European Conference on Design Automation. IEEE Computer Society Press, February 1993.

    Google Scholar 

  7. M. W. Riege and Ph. W. Besslich. Low-complexity synthesis of incompletely specified multiple-output mod-2 sums. IEE Proceedings Part E, Computers and Digital Techniques, 139(4):355–362, July 1992.

    Google Scholar 

  8. J. M. Saul. An improved algorithm for the minimization of mixed polarity Reed-Muller representations. In Proceedings of the IEEE International Conference on Computer Design, pages 372–375. IEEE Computer Society Press, September 1990.

    Google Scholar 

  9. J. M. Saul. An algorithm for the multi-level minimization of Reed-Muller representations. In Proceedings of the IEEE International Conference on Computer Design, pages 634–637. IEEE Computer Society Press, October 1991.

    Google Scholar 

  10. J.M. Saul. Towards a mixed exclusive-/inclusive-or factored form. In IFIP Workshop on Applications of the Reed-Muller Expansion in Circuit Design, pages 1–5, September 1993.

    Google Scholar 

  11. E.M. Sentovich, K.J. Singh, C. Moon, H. Savoj, R.K. Brayton, and A. Sangiovanni-Vincentelli. Sequential Circuit Design Using Synthesis and Optimization. In Proceedings of the International Conference on Computer Design, pages 328–333. IEEE Computer Society Press, October 1992.

    Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Editor information

Reiner W. Hartenstein Manfred Glesner

Rights and permissions

Reprints and permissions

Copyright information

© 1996 Springer-Verlag Berlin Heidelberg

About this paper

Cite this paper

Lester, N., Saul, J. (1996). Logic synthesis for FPGAs using a mixed exclusive-/inclusive-OR form. In: Hartenstein, R.W., Glesner, M. (eds) Field-Programmable Logic Smart Applications, New Paradigms and Compilers. FPL 1996. Lecture Notes in Computer Science, vol 1142. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-61730-2_19

Download citation

  • DOI: https://doi.org/10.1007/3-540-61730-2_19

  • Published:

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-61730-3

  • Online ISBN: 978-3-540-70670-0

  • eBook Packages: Springer Book Archive

Publish with us

Policies and ethics