Abstract
The paper describes the problems associated with the phenomena of metastability in clock edge-triggered flip-flop designs in PLD (Programmable Logic Devices) architecture. The metastability probability, which is dependent on functionality speed, characteristics of integrated circuit technology, design methodology and effects of environmental conditions is discussed. The evaluation of the MTBF (Mean Time Between Failure characteristics of PLD is done, based on the propagation delay distribution measurement of bistable output in the circumstances of deliberately inducing metastable behaviour. The testing results help in design, examine and to predict required MTBF in logic circuits design targeted for PLD. The proper design methodology that would help to virtually overcome the metastability problem is discussed.
This is a preview of subscription content, log in via an institution to check access.
Preview
Unable to display preview. Download preview PDF.
References
M. Pechouček: Anomalous Response Time of Input Synchronizers. IEEE Transactions on Computers, Vol. 25, February 1976, pp. 133–139.
J. Beaston and R. S. Tetrick: Design Confront Metastability in Broadband and Buses. Computer Design, No. 67, March 1986, pp. 67–71.
E. Mayer: Tools help eliminate PLD timing errors. Computer Design, April 1990, pp. 55–64.
R. K. Breuninger and K. Frank: Metastable Characteristics of Texas Instruments Advanced Bipolar Logic Families. The TTL Data Book, Vol. 2, 1985, 7.1–7.8.
K. Nootbaar: Design, testing and application of a metastable-hardened flip-flop. Profession Program Session, Record 16, Wescon 87, November 1987, pp. 16/2, Electronic Conventions Management, Los Angeles, California 90045.
T.C. Tang: Experimental Studies of Metastability Behaviors of Sub-Micron CMOS ASIC Flip Flops. LSI Logic.
D.C. Doughty and S. Lemon: Asynchronous Inputs and Flip-Flop Metastability in the CLAS Trigger at CEBAF. IEEE Transactions on Nuclear Science, Vol. 40, August 1993, pp. 680–684.
B. Medved Rogina and B. Vojnović: Metastability Evaluation Method by Propagation Delay Distribution Measurement. Proceedings of the Fourth Asian Test Symposium, Bangalore, India, November 1995, pp. 40–44.
T.J. Chaney: Measured Flip-Flop Responses to Marginal Triggering. IEEE Transactions on Computers, Vol. 32, December 1983, pp. 1207–1209.
J. U. Horstmann, H. W. Eichel and R. L. Coates: Metastability Behavior of CMOS ASIC Flip-Flops in Theory and Test. IEEE Journal of Solid-State Circuits, Vol. 24, 1989, pp. 146–157.
K. Skala: Optical Information Driven Configurable Hardware. Optical Computing and Processing, Vol. 2, 1992, pp. 63–65.
Author information
Authors and Affiliations
Editor information
Rights and permissions
Copyright information
© 1996 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Rogina, B.M., Skala, K., Vojnović, B. (1996). Metastability characteristics testing for programmable logic design. In: Hartenstein, R.W., Glesner, M. (eds) Field-Programmable Logic Smart Applications, New Paradigms and Compilers. FPL 1996. Lecture Notes in Computer Science, vol 1142. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-61730-2_43
Download citation
DOI: https://doi.org/10.1007/3-540-61730-2_43
Published:
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-61730-3
Online ISBN: 978-3-540-70670-0
eBook Packages: Springer Book Archive