The implementation of a field programmable logic based co-processor for the acceleration of discrete event simulators

Abstract

To accelerate a sequential discrete event simulator it is necessary to accelerate the used priority queue algorithm. In first order the used priority queue algorithm must be performant. A hardware implementation of the algorithm will lead to an important acceleration. FPL technology is used to implement a co-processor, that can manage the Fishspear priority queue algorithm efficiently by exploiting parallelism and pipelining. This is achieved by using an MIMD ALU architecture and the concepts action oriented programming,pre-condition evaluation and hierarchical divided state-machine.