Abstract
In this paper we present an approach for handoptimized pipelined FPGA-multipliers, namely carry save array multipliers (CSM). By a detailed adaptation to the underlying architecture of XC4013E-3 FPGAs, we derive high throughput and compact implementation of FPGA-Multipliers. By means of a sophisticated pipelining scheme, clock frequencies of up to 96MHz are achievable for operand's wordthwidth of up to 10 bits.
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© 1997 Springer-Verlag Berlin Heidelberg
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Do, T.T., Kropp, H., Schwiegershausen, M., Pirsch, P. (1997). Implementation of pipelined multipliers on Xilinx FPGAs. In: Luk, W., Cheung, P.Y.K., Glesner, M. (eds) Field-Programmable Logic and Applications. FPL 1997. Lecture Notes in Computer Science, vol 1304. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-63465-7_210
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DOI: https://doi.org/10.1007/3-540-63465-7_210
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Online ISBN: 978-3-540-69557-8
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