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A 800Mpixel/sec reconfigurable image correlator on XC6216

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Field-Programmable Logic and Applications (FPL 1997)

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 1304))

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Abstract

A high performance image correlator design for the XC6200 is discussed. The design correlates a 1602 pixel template against a larger image, loading 16 new pixel values in parallel, at a clock rate of up to 50MHz. The dynamic reconfiguration capabilities of the device are exploited to rapidly reconfigure between hardwired match image templates at the logic level.

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References

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Author information

Authors and Affiliations

  1. Xilinx Development Corporation, 52 Mortonhall Gate, EH16 6TJ, Edinburgh, Scotland

    Tom Kean & Ann Duncan

Authors
  1. Tom Kean
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  2. Ann Duncan
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Editor information

Wayne Luk Peter Y. K. Cheung Manfred Glesner

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© 1997 Springer-Verlag Berlin Heidelberg

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Kean, T., Duncan, A. (1997). A 800Mpixel/sec reconfigurable image correlator on XC6216. In: Luk, W., Cheung, P.Y.K., Glesner, M. (eds) Field-Programmable Logic and Applications. FPL 1997. Lecture Notes in Computer Science, vol 1304. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-63465-7_243

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  • DOI: https://doi.org/10.1007/3-540-63465-7_243

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  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-63465-2

  • Online ISBN: 978-3-540-69557-8

  • eBook Packages: Springer Book Archive

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