Abstract
Protocol Boosters are functional elements, inserted and deleted from network protocol stacks on an as-needed basis. The Protocol Booster design methodology attempts to improve end-to-end networking performance by adapting protocols to network dynamics.
We describe a new dynamically reconfigurable FPGA based architecture, called the Programmable Protocol Processing Pipeline (P4), which provides a platform for highly-flexible hardware implementations of Protocol Boosters. The prototype P4 is designed to interface to an OC3 (155 Mb/s) ATM link and perform selected boosting functions at this line rate.
The FPGA devices process the data stream as a pipeline of processing elements. Processing elements are downloaded and activated dynamically, based on policies used by the controller to choose configurations. As modules become unnecessary they are removed from the pipeline chain.
This research was supported by DARPA under Contracts #NCR95-20963 and #DABT63-95-C-0073, the AT&T Foundation, the Hewlett-Packard Corporation, the Intel Corporation and the Altera University Grants Program.
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© 1997 Springer-Verlag Berlin Heidelberg
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Hadžić, I., Smith, J.M. (1997). P4: A platform for FPGA implementation of protocol boosters. In: Luk, W., Cheung, P.Y.K., Glesner, M. (eds) Field-Programmable Logic and Applications. FPL 1997. Lecture Notes in Computer Science, vol 1304. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-63465-7_249
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DOI: https://doi.org/10.1007/3-540-63465-7_249
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