Abstract
Fractal image compression technique provides very high compression ratios for natural scenes and has the advantage of being resolution independent. However, the encoding process based on the self-similarity search between range and domain blocks is very computationally intensive. This prohibits their real-time application. In this paper, we first propose two parallel schemes and then present one of the parallel implementations on multiple DSP cards. This card is developed for use as a low-cost, general-purpose digital signal-processing card for ISA bus systems. The experimental results show that the proposed parallel implementation yields a significant speedup compared with serial computation. This implementation provides a cost-effective solution for speeding up the fractal image compression and makes it competitive with other methods.
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References
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© 1997 Springer-Verlag Berlin Heidelberg
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Chow, S.K., Gillies, M., Chan, S.L. (1997). Parallel implementation of fractal image compression using multiple digital signal processors. In: Chin, R., Pong, TC. (eds) Computer Vision — ACCV'98. ACCV 1998. Lecture Notes in Computer Science, vol 1351. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-63930-6_186
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DOI: https://doi.org/10.1007/3-540-63930-6_186
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