Abstract
As high performance parallel computing architectures make their way into systems with tight size, weight, power, and energy budgets (e.g., portable computing and communications, autonomous vehicles, and space-borne computing), compact and efficient computing and communication mechanisms will be required. To provide such a communication mechanism, the Portable Image Computing Architectures (PICA) group at Georgia Tech is designing the High-Performance Efficient Router (HiPER), a multidimensional router with high-throughput serial channels (1-2 Gbps). Providing high performance for size, weight, power, and energy constrained systems requires careful attention to routing, switching, and error control mechanisms, and the HiPER Prototype (HiPER-P) is a proof-of-concept vehicle that will validate efficient implementations of these mechanisms. The HiPER-P combines mad postman (bit- pipelined) switching with dimension-order routing, producing a router with a very low-latency routing function. To maintain robust communication as link speeds increase and link power budgets decrease, the HiPER-P provides flit-level hop-by-hop retransmission of erroneous flits. This error control mechanism provides built-in error control at the network level. The design of the HiPER-P is presented in this paper as well as results of performance simulations which characterize mad postman switching combined with flit-level error control.
This work is supported by NSF contracts #ECS-9422552, EEC-9402723, and ECS-9058144
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References
H. B. Bakoglu, Circuits, Interconnections, and Packaging for VLSI, Addison-Wesley Publishing Company, Reading, MA, 1990.
A. Bellaouar and M. Elmasry, Low-Power Digital VLSI Design: Circuits and Systems, Kluwer Academic Publishers, Boston, MA, 1995.
R. W. Broderson and A. P. Chandrakasan, Low-Power Digital VLSI Design, Kluwer Academic Publishers, Boston, MA, 1995.
A. B. Carlson, Communication Systems: An Introduction to Signals and Noise in Electrical Communication, McGraw Hill, New York, NY, 1986.
A. A. Chien, “A Cost and Speed Model for k-ary n-cube Wormhole Routers,” Proceedings of Hot Interconnects’ 93, August 1993.
W. J. Dally and C. L. Seitz, “The Torus Routing Chip,” Journal of Distributed Computing, vol. 1, no. 3. Pp. 187–196, October, 1986.
W. J. Dally and C. L. Seitz, “Deadlock-free Message Routing on Multiprocessor Interconnection Networks,” IEEE Transactions on Computing, Vol. C-36, no. 5, pp. 547–553, May 1987.
W. J. Dally, “Performance Analysis of k-ary n-cube Interconnection Networks,” IEEE Transactions on Computers, vol. 39, no. 6, pp. 775–785, June 1990.
J. Duato, S. Yalamanchili, L. Ni, Interconnection Networks: An Engineering Approach, Preliminary Manuscript, 1996.
D. Dunning, “Routing Chip Set for the Intel Paragon Supercomputer,” MIT VLSI Seminar Video Tape, 1992.
C. R. Jesshope, P. R. Miller, J. T. Yantchev, “High Performance Communications in Processor Networks,” Proceedings of the 16th International Symposium on Computer Architecture, pp. 150–157, May–June 1989.
P. May, N. M. Jokerst, D. S. Wills, S. Wilkinson, M. Lee, O. Vendier, S. Bond, Z. Hou, G. Dagnall, M. A. Brooke, A. Brown, “Design Issues for Through-Wafer Optoelectronic Multicomputer Interconnects”, In Second International Workshop on Massively Parallel Processing Using Optical Interconnections, pages 8–15, San Antonio, Texas, 23–24 October 1995.
P. May, M. Lee, S. T. Wilkinson, O. Vendier, Z. Ho, S. W. Bond, D. S. Wills, M. Brooke, N. M. Jokerst, and A. Brown, “A 100 Mbps, LED Through-Wafer Optoelectronic Link for Multicomputer Interconnection Networks,” To appear in Journal of Parallel and Distributed Computing, Special Issue on Parallel Computing with Optical Interconnects, 1996.
S. Ramo, J. R. Whinnery, T. VanDuzer, Fields and Waves in Communications Electronics, Second Edition, John Wiley and Sons, New York, NY, 1984.
D. Scott Wills, W. Stephen Lacy, Huy Cat, Michael A. Hopper, Ashutosh Razdan, and Sek M. Chai, “Pica: An Ultra-Light Processor for High-Throughput Applications,” 1993 International Conference on Computer Design, October 3–6, 1993, Cambridge, MA.
E. Winkler, “Escape Routing from Chip Scale Packages,” Proceedings of the 1996 IEEE/CPMT International Manufacturing Technology Symposium, pp. 393–401, 1996.
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© 1998 Springer-Verlag Berlin Heidelberg
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May, P., Chai, S.M., Wills, D.S. (1998). HiPER-P: An Efficient, High-Performance Router for Multicomputer Interconnection Networks. In: Yalamanchili, S., Duato, J. (eds) Parallel Computer Routing and Communication. PCRCW 1997. Lecture Notes in Computer Science, vol 1417. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-69352-1_9
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