Abstract
Test patterns are used to prove the correct functionality and absence of manufacturing faults after producing a chip. The automatic generation of those test patterns for sequential circuits is harder than NP-complete problems and therefore an interesting algorithm to parallelize.
In this paper we describe a parallel approach for automatic test pattern generation (ATPG) using PVM with optimal load balancing. The main advantage over existing approaches is a dynamic solution for partitioning the fault list and the search tree resulting in a very small overhead for communication without the need of any broadcasts and an optimal load balancing without idle times for the test pattern generators.
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© 1996 Springer-Verlag Berlin Heidelberg
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Dahmen, H.C., Gläser, U., Vierhaus, H.T. (1996). Automatic test pattern generation with optimal load balancing. In: Bode, A., Dongarra, J., Ludwig, T., Sunderam, V. (eds) Parallel Virtual Machine — EuroPVM '96. EuroPVM 1996. Lecture Notes in Computer Science, vol 1156. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3540617795_26
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DOI: https://doi.org/10.1007/3540617795_26
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