Definition
The Cydra 5 was a mini-supercomputer designed by Cydrome and completed in 1987. The Cydra 5 heterogeneous multiprocessor consisted of a general-purpose shared-memory multiprocessor based on Motorola 68020 processors along with a numeric processor that used Cydrome’s Directed DataflowTM architecture. The numeric processor achieved about one half the performance of a contemporary supercomputer at about one tenth of the price.
Discussion
Introduction
Cydrome (originally known as Axiom) was founded by chief architect Bob Rau, along with Arun Kumar, Ross Towle, Dave Yen, and Wei Yen. The key design goal for the Cydra 5 was to provide near-supercomputer levels of computing performance at departmental prices. The Cydra 5 was designed to accelerate existing unmodified FORTRAN applications commonly used for scientific computing. Goals included providing 50 (25) MFLOPS of peak single (double) precision floating-point performance and achieving greater computation efficiency by...
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Bibliography
Lam M (1988) Software pipelining: an effective scheduling technique for VLIW machines. In: ACM SIGPLAN ‘88 conference on programming language design and implementation, Atlanta, pp 318–327
Rau BR (1994) Iterative modulo scheduling: an algorithm for software pipelining loops. In: Proceedings of the 27th annual symposium on microarchitecture, San Jose, pp 63–74
Rau BR, Glaeser CD, Greenawalt EM (1982) Architectural support for the efficient generation of code for horizontal achitectures. In: Symposium on architectural support for programming languagges and operating systems, Palo Alto, pp 96–99
Charlesworth AE (1981) An approach to scientific array processing: the architectural design of the AP-120B/FPS-164 family. Computer 4(9):18–27
Fisher JA (1983) Very long instruction word architectures and the the ELI-512. In: Proceedings of the tenth annual symposium on computer architecture, Stockholm, pp 140–150
Davidson ES, Shar LE, Thomas AT, Patel JH (1975) Effective control for pipelined computers. In: Proceedings of the COMPCON, IEEE, New York, pp 181–184
Rau BR, Schlansker MS, Tirumalai PP (1992) Code generation schema for modulo scheduled loops. In: Proceedings of the 25th annual international symposium on microarchitecture, Portland
Rau BR, Schlansker MS, Yen DWL (1989) The Cydra Tm 5 stride-insensitive memory system. In: Proceedings of the 1989 International Conference on Parallel Processing, The Pennsylvania State University, University Park
Dehnert JC, Towle RA (1993) Compiling for the Cydra 5. J Supercomput 7:181–227
Ellis JR (1986) Bulldog: a compiler for VLIW architectures. MIT Press, Cambridge, MA
Schlansker M, Kathail V (1993) Acceleration of first and higher order recurrences on processors with instruction level parallelsim. In: Sixth international workshop on languages and compilers for parallel computing, Portland
Tang J, Davidson ES (1988) An evaluation of the Cray X-MP performance on vectorizable Livermore FORTRAN kernels. In: Proceedings of the 2nd International conference on Supercomputing, ACM, St. Malo
Lowney PG, Freudenberger SM, Karzes TJ, Lichtenstein WD, Nix RP, O’Donnell JS, Ruttenberg JC (1993) The multiflow trace scheduling compiler. J Supercomput 7:51–142
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Schlansker, M. (2011). Cydra 5. In: Padua, D. (eds) Encyclopedia of Parallel Computing. Springer, Boston, MA. https://doi.org/10.1007/978-0-387-09766-4_123
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DOI: https://doi.org/10.1007/978-0-387-09766-4_123
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