Skip to main content

NUMA Caches

  • Reference work entry
Encyclopedia of Parallel Computing

Synonyms

Nonuniform memory access (NUMA) machines

Definition

NUMA is the acronym for Non-Uniform Memory Access. A NUMA cache is a cache memory in which the access time is not uniform but depends on the position of the referred block inside the cache. Among NUMA caches, it possible to distinguish: (1) the NUCA (Non-Uniform Cache Access) architectures, in which the memory space is deeply sub-banked, and the access latency depends on which sub-bank is accessed; and (2) the shared and distributed cache of a tiled Chip Multiprocessor (CMP), in which the latency depends on which cache slice has to be accessed.

Discussion

Introduction

For the past decades, microprocessors’ overall performance has been improved thanks to the continuous reduction of transistor size obtained in silicon fabrication technology. This scaling contributed in both (1) allowing designers to put on a chip more and more transistors, and thus to implement on the same die more and more complex microarchitectures, up to...

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Subscribe and save

Springer+ Basic
$34.99 /Month
  • Get 10 units per month
  • Download Article/Chapter or eBook
  • 1 Unit = 1 Article or 1 Chapter
  • Cancel anytime
Subscribe now

Buy Now

Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

Bibliography

  1. Matzke D (1997) Will physical scalability sabotage performance gains? IEEE Comput 30(9):37–39

    Google Scholar 

  2. Kim C, Burger D, Keckler SW (2003) Non uniform cache architectures for wire-delay dominated on-chip caches. IEEE Micro 23(6):99–107

    Google Scholar 

  3. Chisti Z, Powell MD, Vijaykumar TN (2003) Distance associativity for high-performance energy-efficient non-uniform cache architectures. Proc. 36th int. symp. on microarchitecture. San Diego, CA, pp 55–66

    Google Scholar 

  4. Huh J, Kim C, Shafi H, Zhang L, Bourger D, Keckler SW (2005) A NUCA substrate for flexible CMP cache sharing. Proc. of the 19th int. conf. on supercomputing. Cambridge, MA, pp 20–22

    Google Scholar 

  5. Beckmann BM, Wood DA (2003) Managing wire delay in large chip-multiprocessors caches. Proc. of 37th int. symp. on microarchitecture. San Diego, CA, pp 55–66

    Google Scholar 

  6. Foglia P, Mangano D, Prete CA (2005) A cache design for high performance embedded systems. J Embedded Comput 1(4): 587–598

    Google Scholar 

  7. Foglia P, Mangano D, Prete CA (2005) A NUCA model for embedded systems cache design. IEEE 2005 workshop on embedded systems for real-time multimedia (ESTIMEDIA). New York Metropolitan Area, USA, pp 41–46

    Google Scholar 

  8. Chisti Z, Powell MD, Vijaykumar TN (2005) Optimizing replication, communication, and capacity allocation in CMPs. Proc. of the 32nd int. symp. on computer architecture. Madison

    Google Scholar 

  9. Foglia P, Panicucci F, Prete CA, Solinas M (2009) An evaluation of behaviors of S-NUCA CMPs running scientific workload. Proc. of the 12th euromicro conference on digital system design (DSD). Patras, Greece, pp 26–33

    Google Scholar 

  10. Foglia P, Panicucci F, Prete CA, Solinas M (2009) Analysis of performance dependencies in NUCA-based CMP systems. Proc. of the 21st international symposium on computer architecture and high performance computing (SBAC-PAD), Sao Paulo

    Google Scholar 

  11. Hardavellas N, Ferdman M, Falsafi B, Ailamaki A (2009) Reactive NUCA: near-optimal block placement and replication in distributed caches. Proc. of the 36th international symposium on computer architecture (ISCA-09). Austin, pp 184–195

    Google Scholar 

  12. Merino J, Puente V, Prieto P, Gregorio JÁ (2008) SP-NUCA: a cost effective dynamic non-uniform cache architecture. ACM SIGARCH Computer Architecture News 36(2):64–71, New York

    Google Scholar 

  13. Hammoud M, Cho S, Melhem R (2009) ACM: an efficient approach for managing shared caches in chip multiprocessors. Proc. 4th int. conf. on high performance embedded architectures and compilers (HiPEAC-09). Paphos, Cyprus, pp 355–372

    Google Scholar 

  14. Bardine A, Foglia P, Gabrielli G, Prete CA (2007) Analysis of static and dynamic energy consumption in NUCA caches: initial results. Proc. of the MEDEA 2007 workshop. Brasov, Romania, pp 105–112

    Google Scholar 

  15. Bardine A, Comparetti M, Foglia P, Gabrielli G, Prete CA (2010) Way-adaptable D-Nuca caches. International Journals of High Performance Systems Architecture 2(3/4):215–228

    Google Scholar 

  16. Bartolini S, Foglia P, Prete CA, Solinas M (2010) Feedback driven restructuring of multi-threaded applications for NUCA cache performance in CMPs. 22nd international symposium on computer architecture and high performance computing. Petropolis, Brazil

    Google Scholar 

  17. Bardine A, Comparetti M, Foglia P, Gabrielli G, Prete CA (2009) Impact of on-chip network parameters on NUCA cache performance. IET Computers & Digital Techniques 3(5):501–512

    Google Scholar 

  18. Foglia P, Monni G, Prete CA, Solinas M (2010) Re-Nuca: boosting CMP performances through block replication. In: 13th EUROMICRO conference on digital system design, architectures, methods and tools (DSD2010), Lille, 1–3 Sep 2010. IEEE CS, Los Alamitos, pp 199–206. ISBN: 978-0-7695-4171-6

    Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Editor information

Editors and Affiliations

Rights and permissions

Reprints and permissions

Copyright information

© 2011 Springer Science+Business Media, LLC

About this entry

Cite this entry

Bardine, A., Foglia, P., Prete, C.A., Solinas, M. (2011). NUMA Caches. In: Padua, D. (eds) Encyclopedia of Parallel Computing. Springer, Boston, MA. https://doi.org/10.1007/978-0-387-09766-4_16

Download citation

Publish with us

Policies and ethics