Definition
A shared-memory multiprocessor system provides a global address space in which processors can exchange information and synchronize with one another. When shared variables are cached in multiple caches simultaneously, a memory store operation performed by one processor can make data copies of the same variable in other caches out of date. Cache coherence ensures a coherent memory image for the system so that each processor can observe the semantic effect of memory access operations performed by other processors in time.
Discussion
The cache coherence mechanism plays a crucial role in the construction of a shared-memory system, because of its profound impact on the overall performance and implementation complexity. It is also one of the most complicated problems in the design, because an efficient cache coherence protocol usually incorporates various optimizations.
Cache Coherence and Memory Consistency
The cache coherence protocol of a shared-memory multiprocessor system...
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Bibliography
Lamport L (1979) How to make a multiprocessor computer that correctly executes multiprocess programs. IEEE Trans Comput C-28(9):690–691
May C, Silha E, Simpson R, Warren H (1994) The powerPC architecture: a specification for a new family of RISC processors. Morgan Kaufmann, San Francisco
Intel Corporation (1999) IA-64 application developer’s architecture guide
Gniady C, Falsafi B, Vijaykumar T (1999) Is SC+ILP=RC? In: Proceedings of the 26th annual international symposium on computer architecture (ISCA 1999), Atlanta, 2–4 May 1999, pp 162–17
Tendler J, Dodson J, Fields J, Le H, Sinharoy B (2002) POWER-4 system microarchitecture. IBM J Res Dev 46(1):5
Chaiken D, Fields C, Kurihara K, Agarwal A (1990) Directory-based cache coherence in large-scale multiprocessors. Computer 23(6):49–58
Martin M, Hill M, Wood D (2003) Token coherence: decoupling performance and corrections. In: Proceedings of the 30th annual international symposium on computer architecture international symposium on computer architecture, San Diego, 9–11 June 2003
Strauss K, Shen X, Torrellas J (2007) Uncorq: unconstrained snoop request delivery in embedded-ring multiprocessors. In: Proceedings of the 40th annual IEEE/ACM international symposium on microarchitecture, Chicago, pp 327–342, 1–5 Dec 2007
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Shen, X. (2011). Cache Coherence. In: Padua, D. (eds) Encyclopedia of Parallel Computing. Springer, Boston, MA. https://doi.org/10.1007/978-0-387-09766-4_375
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