Definition
A Systolic Array is a collection of processing elements, called cells, that implements an algorithm by rhythmically computing and transmitting data from cell to cell using only local communication. Cells of a Systolic Array are arranged and connected in a regular pattern with a design that emphasizes a balance between computational and communicational capabilities. Systolic Arrays have proven particularly effective for real-time applications in signal and image processing.
Systolic Algorithms are algorithms specifically designed to make effective use of Systolic Arrays. Systolic Algorithms have also been shown to make particularly efficient use of many general-purpose parallel computers.
The name Systolic Arraysderives from an analogy with the regular pumping of blood by the heart. Systolic, in medical terms, refers to the phase of blood circulation in which the pumping chambers...
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Bibliography
Cloud EL (1988) Frontiers of massively parallel computation. In: Proceedings of the 2nd symposium on the frontiers of massively parallel computation, Fairfax, VA, pp 373–381
Cragon HG (2003) From fish to colossus: how the German Lorenz cipher was broken at Bletchley park. Cragon Books, Dallas, ISBN: 0-9743045-0-6
Frank GA, Greenawalt EM, Kulkarni AV (1982) A systolic processor for signal processing. In: Proceedings of AFIPS ’82, June 7–10. ACM, New York, pp 225–231
Fisher AL, Kung HT, Monier LM, Dohi Y (1983) Architecture of the PSC: a programmable systolic chip. In: Proceedings of the 10th annual international symposium on computer architecture (ISCA ’83), Stockholm, Sweden. ACM, New York, Vol 11, Issue 3, pp 48–53
Gross T, O’Hallaron DR (1998) iWarp: anatomy of a parallel computing system. MIT Press, Cambridge, MA, 488 p
Kung HT, Leiserson CE (1978) Systolic arrays (for VLSI). In: Duff IS, Stewart GW (eds) Proceedings of sparse matrix proceedings 1978. Society for Industrial and Applied Mathematics (SIAM), Philadelphia, PA, pp 256–282
Kung HT, Song SW (1981) A systolic 2-D convolution chip. In: Proceedings of 1981 IEEE computer society workshop on computer architecture for pattern analysis and image database management, 11–13 Nov 1981, Hot Springs, Virginia, pp 159–160
Kung HT (1982) Why systolic architectures? IEEE Comput 15(1):37–46
Kung SY (1988) VLSI array processors. Prentice Hall, Upper Saddle River
Mead C, Conway L (1980) Chap. 8, Highly concurrent systems. In: Introduction to VLSI systems. Addison-Westey series in computer science, Addison-Wesley, Menlo Park, CA, pp 263–332
Tirpak FM Jr (1991) Software development on the high-speed systolic array processor (HISSAP): lessons learned. Technical report 1429. Naval Ocean Systems Center, San Diego, CA
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Reinders, J.R. (2011). Systolic Arrays. In: Padua, D. (eds) Encyclopedia of Parallel Computing. Springer, Boston, MA. https://doi.org/10.1007/978-0-387-09766-4_467
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