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Floorplan and Placement

1994; Kajitani, Nakatake, Murata, Fujiyoshi

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Encyclopedia of Algorithms

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Keywords and Synonyms

Layout ; Alignment ; Packing; Dissection

Problem Definition

The problem is concerned with efficient coding of the constraint that defines the placement of objects on a plane without mutual overlapping. This has numerous motivations, especially in the design automation of integrated semiconductor chips, where almost hundreds of millions of rectangular modules shall be placed within a small rectangular area (chip). Until 1994, the only known coding efficient in computer aided design was Polish‐Expression [1]. However, this can only handle a limited class of placements of the slicing structure. In 1994 Nakatake, Fujiyoshi, Murata, and Kajitani [2], and Murata, Fujiyoshi, Nakatake, and Kajitani [3] were finally successful to answer this longstanding problem in two contrasting ways. Their code names are Bounded‐Sliceline-Grid (BSG) for floorplanning and Sequence-Pair(SP) for placement....

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Recommended Reading

  1. Wong, D.F., Liu, C.L.: A new algorithm for floorplan design. In: ACM/IEEE Design Automation Conference (DAC), November 1985, 23rd, pp. 101–107

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  2. Nakatake, S., Murata, H., Fujiyoshi, K., Kajitani, Y.: Bounded Sliceline Grid (BSG) for module packing. IEICE Technical Report, October 1994, VLD94-66, vol. 94, no. 313, pp. 19–24 (in Japanese)

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  3. Murata, H., Fujiyoshi, K., Nakatake, S., Kajitani, Y.: A solution space of size (n!)2 for optimal rectangle packing. In: 8th Karuizawa Workshop on Circuits and Systems, April 1995, pp. 109–114

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  4. Murata, H., Nakatake, S., Fujiyoshi, K., Kajitani, Y.: VLSI Module placement based on rectangle‐packing by Sequence-Pair. IEEE Trans. Comput. Aided Design (TCAD) 15(12), 1518–1524 (1996)

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  5. Nakatake, S., Fujiyoshi, K., Murata, H., Kajitani, Y.: Module packing based on the BSG‐structure and IC layout applications. IEEE TCAD 17(6), 519–530 (1998)

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  6. Guo, P.N., Cheng, C.K., Yoshimura, T.: An O‑tree representation of non-slicing floorplan and its applications. In: 36th DAC., June 1998, pp. 268–273

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  7. Hong, X., Dong, S., Ma, Y., Cai, Y., Cheng, C.K., Gu, J.: Corner Block List: An efficient topological representation of non-slicing floorplan. In: International Computer Aided Design (ICCAD) '00, November 2000, pp. 8–12,

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  8. Chang, Y.-C., Chang, Y.-W., Wu, G.-M., Wu, S.-W.: B*-trees: A new representation for non-slicing floorplans. In: 37th DAC, June 2000, pp. 458–463

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  9. Sakanushi, K., Kajitani, Y., Mehta, D.: The quarter-state-sequence floorplan representation. In: IEEE TCAS-I: 50(3), 376–386 (2003)

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  10. Kodama, C., Fujiyoshi, K.: Selected Sequence-Pair: An efficient decodable packing representation in linear time using Sequence-Pair. In: Proc. ASP-DAC 2003, pp. 331–337

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  11. Kajitani, Y.: Theory of placement by Single‐Sequence Realted with DAG, SP, BSG, and O‑tree. In: International Symposium on Circuts and Systems, May 2006

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  12. Imahori, S.: Privatre communication, December 2005

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Author information

Authors and Affiliations

  1. Department of Information and Media Sciences, The University of Kitakyushu, Kitakyushu, Japan

    Yoji Kajitani

Authors
  1. Yoji Kajitani
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Editor information

Editors and Affiliations

  1. Department of Electrical Engineering and Computer ScienceMcCormick School of Engineering and Applied Science, Northwestern University, Evanston, IL, 60208, USA

    Ming-Yang Kao Professor of Computer Science

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© 2008 Springer-Verlag

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Kajitani, Y. (2008). Floorplan and Placement. In: Kao, MY. (eds) Encyclopedia of Algorithms. Springer, Boston, MA. https://doi.org/10.1007/978-0-387-30162-4_145

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