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Gate Sizing

2002; Sundararajan, Sapatnekar, Parhi

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Encyclopedia of Algorithms

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Keywords and Synonyms

Fast and exact transistor sizing          

Problem Definition

Table 1 Comparison of TILOS and MINFLOTRANSIT on a Sun Ultrasparc 10 workstation for ISCAS85 and MCNC91 benchmarks for 0.13 um technology. The delay specs. are with respect to a minimum-sized circuit. The optimization approach followed here was gate sizing
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Recommended Reading

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  15. Sundararajan, V., Sapatnekar, S.S., Parhi, K.K.: Fast and exact transistor sizing based on iterative relaxation. Computer-Aided Design of Integrated Circuits and Systems, IEEE Trans. 21(5),568–581 (2002)

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Authors and Affiliations

  1. Texas Instruments, Dallas, TX, USA

    Vijay Sundararajan

Authors
  1. Vijay Sundararajan
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Editors and Affiliations

  1. Department of Electrical Engineering and Computer ScienceMcCormick School of Engineering and Applied Science, Northwestern University, Evanston, IL, 60208, USA

    Ming-Yang Kao Professor of Computer Science

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Sundararajan, V. (2008). Gate Sizing. In: Kao, MY. (eds) Encyclopedia of Algorithms. Springer, Boston, MA. https://doi.org/10.1007/978-0-387-30162-4_159

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