Keywords and Synonyms
Library-based technology mapping; Technology dependent optimization
Problem Definition
Technology mapping is the problem of implementing a sequential circuit using the gates of a particular technology library. It is an integral component of any automated VLSI circuit design flow. In the prototypical chip design flow, combinational logic gates and sequential memory elements are composed to form sequential circuits. These circuits are subject to various logic optimizations to minimize area, delay, power and other performance metrics. The resulting optimized circuits still consist of primitive logic functions such as AND and OR gates. The next step is to efficiently realize these circuits in a specific VLSI technology using a library of gates available from the semiconductor vendor. Such a library would typically consist of gates of varying sizes and speeds for primitive logic functions, (AND and OR) and more complex functions (exclusive-OR, multiplexer). However,...
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Recommended Reading
Aho, A., Sethi, R., Ullman, J.: Compilers: Principles, Techniques and Tools. pp. 557–584. Addison Wesley, Boston (1986)
Aho, A., Johnson, S.: Optimal Code Generation for Expression Trees. J. ACM 23(July), 488–501 (1976)
Darringer, J.A., Brand, D., Gerbi, J.V., Joyner, W.H., Trevillyan, L.H.: LSS: Logic Synthesis through Local Transformations. IBM J. Res. Dev. 25, 272–280 (1981)
Keutzer, K.: DAGON: Technology Binding and Local Optimizations by DAG Matching. In: Proc. of the 24th Design Automation Conference 28(1), pp. 341–347. Miami Beach, June 1987
Rudell, R.: Logic Synthesis for VLSI Design. Ph. D. thesis, University of California at Berkeley, ERL Memo 89/49, April 1989
Sentovich, E.M., Singh, K.J., Moon, C., Savoj, H., Brayton, R.K., Sangiovanni‐Vincentelli, A.: Sequential Circuit Design using Synthesis and Optimization. In: Proc. of the IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD), pp. 328–333. Cambridge, October 1992
Cong, J., Ding, Y.: An Optimal Technology Mapping Algorithm for Delay Optimization in Lookup-Table based FPGA Designs. In: Proc. of the 1992 IEEE/ACM International Conference on Computer-Aided Design (ICCAD-92) 8(12), pp. 48–53, November 1992
Tiwari, V., Ashar, P., Malik, S.: Technology Mapping for Low Power in Logic Synthesis. Integr. VLSI J. 20(3), 243–268 (1996)
Lehman, E., Watanabe, Y., Grodstein, J., Harkness, H.: Logic Decomposition during Technology Mapping. IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 16(8), 813–834, (1997)
Kutzschebauch, T., Stok, L.: Congestion Aware Layout Driven Logic Synthesis. In: Proc. of the IEEE/ACM International Conference on Computer-Aided Design, 2001, pp. 216–223
Devadas, S., Ghosh, A., Keutzer, K.: Logic Synthesis. McGraw Hill, New York (1994). pp. 185–200
De Micheli, G.: Synthesis and Optimization of Digital Circuits, 1st edn., pp. 504–533. McGraw-Hill, New York (1994)
Stok, L., Tiwari, V.: Technology Mapping. In: Hassoun, S., Sasou, T. (eds.) Logic Synthesis and Verification, pp. 115–139. Kluwer International Series In Engineering And Coputer Science Series. Kluwer Academic Publisher, Norwell (2002)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2008 Springer-Verlag
About this entry
Cite this entry
Keutzer, K., Ravindran, K. (2008). Technology Mapping. In: Kao, MY. (eds) Encyclopedia of Algorithms. Springer, Boston, MA. https://doi.org/10.1007/978-0-387-30162-4_420
Download citation
DOI: https://doi.org/10.1007/978-0-387-30162-4_420
Publisher Name: Springer, Boston, MA
Print ISBN: 978-0-387-30770-1
Online ISBN: 978-0-387-30162-4
eBook Packages: Computer ScienceReference Module Computer Science and Engineering