Benchmarks can contribute significantly to algorithm development of many fields by providing a common basis for quantitative measurement and comparison. The early MCNC benchmarks and ISPD98 benchmarks [1] helped the academic community significantly to measure the advances in physical design in 1990s. While still being used extensively in placement and floorplanning research, those benchmarks can no longer be considered representative of today’s physical design challenges. To further aid future advances in placement, new benchmark suites, dubbed as ISPD 2005/2006 Placement Benchmarks, have been released in conjunction with ISPD placement contests. There are total 16 benchmark circuits that are directly derived from modern industrial ASIC designs.
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References
C. Alpert, “The ISPD98 Circuit Benchmark Suite,” in Proc. ACM/IEEE International Symposium on Physical Design, 1998, pp. 80-85
A. Agnihotri, S. Ono and P. Madden, “Recursive Bisection Placement: Feng Shui 5.0 Implementation Details,” in Proc. ACM/IEEE International Symposium on Physical Design, 2005, pp. 230-232
A.E. Caldwell, A.B. Kahng, I.L. Markov, VLSI cad bookshelf. http://vlsicad. eecs.umich.edu/BK/. See also Caldwell AE, Kahng AB, Markov IL (2002) Toward cad-ip reuse: the marco gsrc bookshelf of fundamental cad algorithms. IEEE Design and Test 72-81
T.F. Chan, J. Cong, M. Romesis, J.R. Shinnerl, K. Sze and M. Xie, “mPL6: A Robust Multilevel Mixed-Size Placement Engine,” in Proc. ACM/IEEE International Symposium on Physical Design, 2005, pp. 227-229
T.F. Chan, J. Cong, J.R. Shinnerl, K. Sze and M. Xie, “mPL6: Enhanced Multilevel Mixed-Size Placement,” in Proc. ACM/IEEE International Symposium on Physical Design, 2006, pp. 212-214
T.-C. Chen, T.-C. Hsu, Z.-W. Jiang and Y.-W. Chang, “NTUplace: A Ratio Partitioning Based Placement Algorithm for Large-Scale Mixed-Size Designs,” in Proc. ACM/IEEE International Symposium on Physical Design, 2005, pp. 236-238
Z.-W. Jiang, T.-C. Chen, T.-C. Hsu, H.-C. Chen and Y.-W. Chang, “NTUplace2: A Hybrid Placer Using Partitioning and Analytical Techniques,” in Proc. ACM/IEEE International Symposium on Physical Design, 2006, pp. 215-217
B. Hu, Y. Zeng and M. Marek-Sadowska, “mFAR: Fixed-Points-Addtion-Based VLSI Placement Algorithm,” Proc. ACM/IEEE International Symposium on Physical Design, 2005, pp. 239-241
A.B. Kahng, S. Reda, and Q. Wang, “APlace: A General Analytic Placement Framework,” in Proc. ACM/IEEE International Symposium on Physical Design, 2005, pp. 233-235
A.B. Kahng, and Q. Wang, “A Faster Implementation of APlace,” in Proc. ACM/IEEE International Symposium on Physical Design, 2006, pp. 218-220
G.-J. Nam, C.J. Alpert, P. Villarrubia, B. Winter and M. Yildiz, “The ISPD2005 Placement Contest and Benchmark Suite,”, in Proc. ACM/IEEE International Symposium on Physical Design, 2005, pp. 216-220
Gi-Joon Nam, “ISPD 2006 placement contest: Benchmark suite and results,” Proceedings of the International Symposium on Physical Design, pages 167-167, 2006
B. Obermeier, H. Ranke and F. M. Johannes, “Kraftwerk - A Versatile Placement Approach,” in Proc. ACM/IEEE International Symposium on Physical Design, 2005, pp. 242-244
J.A. Roy, D.A. Papa, S.N. Adya, H.H. Chan A.N. Ng, J.F. Lu and I.L. Markov, “Capo: Robust and Scalable Open-Source Min-Cut Floorplacer,” in Proc. ACM/IEEE International Symposium on Physical Design, 2005, pp. 224-226
J.A. Roy, D.A. Papa, A.N. Ng and I.L. Markov, “Satisfying Whitespace Requirements in Top-down Placement,” in Proc. ACM/IEEE International Symposium on Physical Design, 2006, pp. 206-28
T. Taghavi, X. Yang, B.K. Choi, M. Wang and M. Sarrafzadeh, “DRAGON2005: LargeScale Mixed-Size Placement Tool,” in Proc. ACM/IEEE International Symposium on Physical Design, 2005, pp. 245-247
T. Taghavi, X. Yang, B.K. Choi, M. Wang and M. Sarrafzadeh, “DRAGON2006: Blockage-Aware Congestion-Controlling Mixed-Size Placer,” in Proc. ACM/IEEE International Symposium on Physical Design, 2006, pp. 209-211
N. Viswanathan, M. Pan and C.C. -N. Chu, “FastPlace: An Analytical Placer for MixedMode Designs,” in Proc. ACM/IEEE International Symposium on Physical Design, 2005, pp. 221-223
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Nam, GJ., Alpert, C.J., Villarrubia, P.G. (2007). ISPD 2005/2006 Placement Benchmarks. In: Nam, GJ., Cong, J. (eds) Modern Circuit Placement. Series on Integrated Circuits and Systems. Springer, Boston, MA. https://doi.org/10.1007/978-0-387-68739-1_1
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