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mPL6: Enhanced Multilevel Mixed-Size Placement with Congestion Control

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Modern Circuit Placement

Part of the book series: Series on Integrated Circuits and Systems ((ICIR))

mPL6 consists of three basic ingredients: global placement by multilevel nonlinear programming [21], discrete graph-based macro legalization followed by linear-time scan-based standard-cell legalization [26], and detailed placement [26]. It is designed for speed and scalability, low wirelength results, adaptability to complex constraints, and robustness under low white space.

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Author information

Authors and Affiliations

  1. 90095-1555, Los Angeles, CA

    Tony F. Chan & Kenton Sze

  2. 90095-1596, Los Angeles, CA

    Joseph R. Shinnerl & Min Xie

Authors
  1. Tony F. Chan
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  2. Kenton Sze
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  3. Joseph R. Shinnerl
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  4. Min Xie
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Editor information

Editors and Affiliations

  1. IBM Austin Research Laboratory, Austin, TX, USA

    Gi-Joon Nam

  2. University of California, Los Angeles, CA, USA

    Jason Cong

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Chan, T.F., Sze, K., Shinnerl, J.R., Xie, M. (2007). mPL6: Enhanced Multilevel Mixed-Size Placement with Congestion Control. In: Nam, GJ., Cong, J. (eds) Modern Circuit Placement. Series on Integrated Circuits and Systems. Springer, Boston, MA. https://doi.org/10.1007/978-0-387-68739-1_10

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  • DOI: https://doi.org/10.1007/978-0-387-68739-1_10

  • Publisher Name: Springer, Boston, MA

  • Print ISBN: 978-0-387-36837-5

  • Online ISBN: 978-0-387-68739-1

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