Although circuit placement has been studied for decades, it continuously attracts research attentions. The placement problems grow rapidly in both problem size and complexity. Some industry placement problems contain multimillion gates and excessive number of blockages [1,2]. In this chapter, we introduce DPlace, an anchor cell and diffusion spreading-based quadratic placement engine that can handle largescale placement problem.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
Similar content being viewed by others
References
G.-J. Nam, C. J. Alpert, P. Villarrubia, B. Winter, and M. Yildiz, “The ispd2005 placement contest and benchmark suite,” in Proc. Int. Symp. on Physical Design, (New York, NY, USA), pp. 216-220, ACM, 2005
G.-J. Nam, “Ispd 2006 placement contest: Benchmark suite and results,” in Proc. Int. Symp. on Physical Design, (New York, NY, USA), pp. 167-167, ACM, 2006
TimberWolf Systems, Inc., “Timberwolf placement & global routing software package,” in http://www2.twolf.com/benchmark.html
A.E. Caldwell, A.B. Kahng, and I.L.Markov, “Can recursive bisection alone produce routable, placements?,” in Proc. Design Automation Conf., pp. 477-482, 2000
M. Wang, X. Yang, and M. Sarrafzadeh, “Dragon2000: Standard-cell placement tool for large industry circuits,” in Proc. Int. Conf. on Computer Aided Design, pp. 260-263, 2000
M.C. Yildiz and P.H. Madden, “Improved cut sequences for partitioning based placement,” in Proc. Design Automation Conf., (New York, NY, USA), pp. 776-779, ACM, 2001
J. Kleinhans, G. Sigl, F.M. Johannes, and K. Antreich, “GORDIAN: VLSI placement by quadratic programming and slicing optimization,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. CAD-10, pp. 356-365, March 1991
H. Eisenmann and F. M. Johannes, “Generic global placement and floorplanning,” in Proc. Design Automation Conf., pp. 269-274, 1998
B. Hu and M. Marek-Sadowska, “Far: fixed-points addition & relaxation based placement,” in Proc. Int. Symp. on Physical Design, (New York, NY, USA), pp. 161-166, ACM, 2002
A.B. Kahng and Q. Wang, “An analytic placer for mixed-size placement and timingdriven placement,” in Proc. Int. Conf. on Computer Aided Design, pp. 565-572, November 2004
N. Viswanathan and C.C.N. Chu, “Fastplace: Efficient analytical placement using cell shifting, iterative local refinement and a hybrid net model,” in Proc. Int. Symp. on Physical Design, pp. 26-33, 2004
K. Vorwerk, A. Kennings, and A. Vannelli, “Engineering details of a stable force-directed placer,” in Proc. Int. Conf. on Computer Aided Design, 2004
T. Chan, J. Cong, and K. Sze, “Multilevel generalized force-directed method for circuit placement,” in Proc. Int. Symp. on Physical Design, 2005
B. Yao, H. Chen, C.-K. Cheng, N.-C. Chou, L.-T. Liu, and P. Suaris, “Unified quadratic programming approach for mixed mode placement,” in Proc. Int. Symp. on Physical Design, 2005
ISPD 2005 Placement Contest, “http://www.sigda.org/ispd2005/ispd05/slides/10-1-placement-contest-ispd05.ppt,” 2005
A.B. Kahng, S. Reda, and Q. Wang, “Aplace: A general analytic placement framework,” in Proc. Int. Symp. on Physical Design, pp. 233-235, April 2005
T.-C. Chen, Z.-W. Jiang, T.-C. Hsu, H.-C. Chen, and Y.-W. Chang, “A high quality analytical placer considering preplaced blocks and density constraint,” in Proc. Int. Conf. on Computer Aided Design, 2006
W.C. Naylor, R. Donelly, and L. Sha”, “Non-linear optimization system and method for wire length and dealy optimization for an automatic electric circuit placer,” US patent 6,301,693,2001
T. Luo and D.Z. Pan, “Large scale placement with explicit cell movement control,” in Technical Report UT-CERC-06-01, April 2006
F. Mo, A. Tabbara, and R. K. Brayton, “A force-directed macro-cell placer,” in Proc. Int. Conf. on Computer Aided Design, p. 4, EECS, UC Berkeley, November 2000 A demo can be found at: http://www-cad.eecs.berkeley.edu/fanmo/PlacementAlgorithm/index.html
ISPD 2002 Benchmark, “http://vlsicad.eecs.umich.edu/bk/ispd02bench/,”
P. Spindler and F. M. Johannes, “Fast and robust quadratic placement combined with an exact linear net model,” in Proc. Int. Conf. on Computer Aided Design, 2006
H. Ren, D. Z. Pan, C. J. Alpert, and P. Villarrubia, “Diffusion-based placement migration,” in Proc. Design Automation Conf., June, 2005
G. Sigl, K. Doll, and F. M. Johannes, “Analytical placement: A linear or a quadratic objective function?,” in DAC ’91: Proc. 28th Conf. on ACM/IEEE Design Automation, (New York, NY, USA), pp. 427-432, ACM, 1991
D. Hill, “Method and system for high speed detailed placement of cells within an integrated circuit design,” US patent 6,370,673, 2002
M. Pan, N. Viswanathan, and C.C.N. Chu, “An efficient and effective. detailed placement algorithm,” in Proc. Int. Conf. on Computer Aided Design, 2005
LASpack, “http://www.mgnet.org/mgnet/codes/laspack/html/laspack.html,” 1995
H. Qian and S.S. Sapatnekar, “A hybrid linear equation solver and its application in quadratic placement,” in Proc. Int. Conf. on Computer Aided Design, 2005
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2007 Springer Science+Business Media, LLC
About this chapter
Cite this chapter
Luo, T., Pan, D.Z. (2007). DPlace: Anchor Cell-Based Quadratic Placement with Linear Objective. In: Nam, GJ., Cong, J. (eds) Modern Circuit Placement. Series on Integrated Circuits and Systems. Springer, Boston, MA. https://doi.org/10.1007/978-0-387-68739-1_3
Download citation
DOI: https://doi.org/10.1007/978-0-387-68739-1_3
Publisher Name: Springer, Boston, MA
Print ISBN: 978-0-387-36837-5
Online ISBN: 978-0-387-68739-1
eBook Packages: EngineeringEngineering (R0)