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Capo: Congestion-Driven Placement for Standard-cell and RTL Netlists with Incremental Capability

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Modern Circuit Placement

Part of the book series: Series on Integrated Circuits and Systems ((ICIR))

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In this chapter, we describe the robust and scalable academic placement tool Capo. Capo uses the min-cut placement paradigm and performs (a) scalable multiway partitioning, (b) routable standard-cell placement, (c) integrated mixed-size placement, (d) wire length-driven fixed-outline floorplanning as well as (e) incremental placement.

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References

  1. Adya SN, Chaturvedi S, Roy JA, Papa DA, Markov IL (2004) Unification of partitioning, placement and floorplanning. In Proc ICCAD 550-557

    Google Scholar 

  2. Adya SN, Markov IL (2003) Fixed-outline floorplanning: enabling hierarchical design. IEEE Trans on VLSI 11(6):1120-1135

    Article  Google Scholar 

  3. Adya SN, Markov IL (2005) Combinatorial techniques for mixed-size placement. ACM Trans on Design Auto of Elec Sys 10(5)

    Google Scholar 

  4. Adya SN, Markov IL, Villarrubia PG (2006) On whitespace and stability in physical synthesis. Integration: the VLSI J 25(4):340-362

    Article  Google Scholar 

  5. Agnihotri A et al. (2003) Fractional cut: improved recursive bisection placement. In Proc ICCAD 307-310

    Google Scholar 

  6. Alpert CJ, Nam G-J, Villarrubia PG, (2003) Effective free space management for cut-based placement via analytical constraint generation. IEEE Trans on CAD 22 (10):1343-1353

    Google Scholar 

  7. Brenner U, Vygen J (2000) Faster optimal single-row placement with fixed ordering. In Proc DATE 117-121

    Google Scholar 

  8. Brenner U, Rohe A (2003) An effective congestion driven placement framework. IEEE Trans. on CAD 22(4):387-394

    Google Scholar 

  9. Caldwell AE, Kahng AB, Mantik S, Markov IL, Zelikovsky A (1999) On wirelength estimations for row-based placement. IEEE Trans on CAD 18(9):1265-1278

    Google Scholar 

  10. Caldwell AE, Kahng AB, Markov IL (2000) Improved algorithms for hypergraph bipartitioning. In Proc ASPDAC 661-666

    Google Scholar 

  11. Caldwell AE, Kahng AB, Markov IL (2000) Can recursive bisection alone produce routable placements? In Proc DAC 477-482

    Google Scholar 

  12. Caldwell AE, Kahng AB, Markov IL (2000) Design and implementation of move-based heuristics for vlsi hypergraph partitioning. ACM J of Experimental Algorithms 5

    Google Scholar 

  13. Caldwell AE, Kahng AB, Markov IL (2000) Optimal partitioners and end-case placers for standard-cell layout. IEEE Trans on CAD 19(11):1304-1314

    Google Scholar 

  14. Caldwell AE, Kahng AB, Markov IL. VLSI cad bookshelf. http://vlsicad. eecs.umich.edu/BK/. See also Caldwell AE, Kahng AB, Markov IL (2002) Toward cad-ip reuse: the marco gsrc bookshelf of fundamental cad algorithms. IEEE Design and Test 72-81

  15. Caldwell AE, Kahng AB, Markov IL (2003) Hierarchical whitespace allocation in top-down placement. IEEE Trans on CAD 22(11):716-724

    Google Scholar 

  16. Chang C-C, Cong J, Romesis M, Xie M (2004) Optimality and scalability study of existing placement algorithms. IEEE Trans on CAD 23(4):537-549

    Google Scholar 

  17. Chen TC, Chang YW, Lin SC (2005) IMF: interconnect-driven multilevel floorplanning for large-scale building-module designs. In Proc ICCAD 159-164

    Google Scholar 

  18. Fiduccia CM, Mattheyses RM (1982) A linear-time heuristic for improving network partitions. In Proc DAC 175-181

    Google Scholar 

  19. Goldberg AV (1997) An efficient implementation of a scaling minimum-cost flow algorithm. ACM J. Algorithms 22:1-29

    Article  Google Scholar 

  20. IWLS 2005 Benchmarks, http://iwls.org/iwls2005/benchmarks.html

  21. Kahng AB, Mantik S, Markov IL, (2002) Min-max placement For large-scale timing optimization. In Proc ISPD 143-148

    Google Scholar 

  22. Kahng AB, Mandoiu II, Zelikovsky A (2003) Highly Scalable Algorithms for rectilinear and octilinear steiner trees. In Proc ASPDAC 827-833

    Google Scholar 

  23. Kahng AB, Wang Q (2005) Implementation and extensibility of an analytic placer. IEEE Trans on CAD 25(5):734-747

    Google Scholar 

  24. Kahng AB, Reda S (2004) Placement feedback: a concept and method for better min-cut placement. In Proc DAC 143-148

    Google Scholar 

  25. Karypis G, Aggarwal R, Kumar V, Shekhar S (1997) Multilevel hypergraph partitioning: applications in vlsi domain. In Proc DAC 526-629

    Google Scholar 

  26. Khatkhate A, Li C, Agnihotri AR, Yildiz MC, Ono S, Koh C-K, Madden PH (2004). Recursive bisection based mixed block placement. In Proc ISPD 84-89

    Google Scholar 

  27. Li C, Xie M, Koh C-K, Cong J, Madden PH (2004) Routability-driven placement and whitespace allocation. In Proc ICCAD 394-401

    Google Scholar 

  28. Li C, Koh C-K, Madden PH (2005) Floorplan management: incremental placement for gate sizing and buffer insertion. In Proc ASPDAC 349-354

    Google Scholar 

  29. Moffitt MD, Ng AN, Markov IL, Pollack ME (2006) Constraint-driven floorplan repair. In Proc DAC 1103-1108

    Google Scholar 

  30. Nam G-J, Alpert CJ, Villarrubia P, Winter B, Yildiz M (2005) The ISPD 2005 placement contest and benchmark suite. In Proc ISPD 216-220

    Google Scholar 

  31. Ng AN, Markov IL, Aggarwal R, Ramachandran V (2006) Solving hard instances of floorplacement. In Proc ISPD 170-177

    Google Scholar 

  32. Papa DA, Adya SN, Markov IL (2004) Constructive benchmarking for placement. In Proc GLSVLSI 113-118 http://vlsicad.eecs.umich.edu/BK/FEATURE/

  33. Reda S, Chowdhary A (2006) Effective linear programming based placement methods. In Proc ISPD 186-191

    Google Scholar 

  34. Roy JA, Adya SN, Papa DA, Markov IL (2006) Min-cut floorplacement. IEEE Trans on CAD 25(7):1313-1326

    Google Scholar 

  35. Roy JA, Markov IL (2007) Seeing the forest and the trees: steiner wirelength optimization in placement. To appear in IEEE Trans on CAD

    Google Scholar 

  36. Roy JA, Markov IL (2007) ECO-system: embracing the change in placement. To appear IEEE Trans on CAD

    Google Scholar 

  37. Roy JA, Papa DA, Ng AN, Markov IL (2006) Satisfying whitespace requirements in top-down placement. In Proc ISPD 206-208

    Google Scholar 

  38. Tang X, Tian R, Wong MDF (2005) Optimal redistribution of whitespace for wirelength minimization. In Proc ASPDAC 412-417

    Google Scholar 

  39. Westra J, Bartels C, Groeneveld P (2004) Probabilistic congestion prediction. In Proc ISPD 204-209

    Google Scholar 

  40. Yang X, Choi B-K, Sarrafzadeh M (2002) Routability driven whitespace allocation for fixed-die standard-cell placement. IEEE Trans on CAD 22(4):410-419

    Google Scholar 

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Roy, J.A., Papa, D.A., Markov, I.L. (2007). Capo: Congestion-Driven Placement for Standard-cell and RTL Netlists with Incremental Capability. In: Nam, GJ., Cong, J. (eds) Modern Circuit Placement. Series on Integrated Circuits and Systems. Springer, Boston, MA. https://doi.org/10.1007/978-0-387-68739-1_5

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  • DOI: https://doi.org/10.1007/978-0-387-68739-1_5

  • Publisher Name: Springer, Boston, MA

  • Print ISBN: 978-0-387-36837-5

  • Online ISBN: 978-0-387-68739-1

  • eBook Packages: EngineeringEngineering (R0)

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