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APlace: A High Quality, Large-Scale Analytical Placer

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Modern Circuit Placement

Part of the book series: Series on Integrated Circuits and Systems ((ICIR))

Modern design requirements have brought additional complexities to netlists and layouts. Millions of components, whitespace resources, and fixed/movable blocks are just a few to mention in the list of complexities.With these complexities in mind, placers are faced with the burden of finding an arrangement of placeable objects under strict wirelength, timing, and power constraints. In this chapter, we describe the architecture and novel details of our high quality, large-scale analytical placer APlace2 (and the subsequent APlace3) [26–28]. The performance of APlace2, has been recognized in the recent ISPD-2005 placement contest, and in this paper we disclose many of the technical details that we believe are key factors to its performance. We describe (1) a new clustering architecture, (2) a dynamically adaptive analytical solver, and (3) better legalization schemes and novel detailed placement methods. We also provide extensive experimental results on a number of benchmark sets, including the IBM ISPD’04, IBM-PLACE 2.0, ICCAD’04, ISPD’05, PEKO’05, ISPD’06, PEKO’06 as well as using the zero-change netlist transformation benchmarking framework.

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Authors
  1. Andrew B. Kahng
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  2. Sherief Reda
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  3. Qinke Wang
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Editor information

Editors and Affiliations

  1. IBM Austin Research Laboratory, Austin, TX, USA

    Gi-Joon Nam

  2. University of California, Los Angeles, CA, USA

    Jason Cong

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Kahng, A.B., Reda, S., Wang, Q. (2007). APlace: A High Quality, Large-Scale Analytical Placer. In: Nam, GJ., Cong, J. (eds) Modern Circuit Placement. Series on Integrated Circuits and Systems. Springer, Boston, MA. https://doi.org/10.1007/978-0-387-68739-1_7

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  • DOI: https://doi.org/10.1007/978-0-387-68739-1_7

  • Publisher Name: Springer, Boston, MA

  • Print ISBN: 978-0-387-36837-5

  • Online ISBN: 978-0-387-68739-1

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