Abstract
In this paper we describe a spatiotemporal parallel algorithm to optimize the power consumption of image processing on FPGA’s. We show how the implementation of our method can significantly reduce power consumption at higher processing speeds compared to traditional spatial (pipeline) parallel processing techniques. We demonstrated a real-time image processing system on a FPGA device and calculated the power consumption. The results show that when the image partitioned into 6 sections the power consumption drops by 45% compared to previous approaches.
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Atabany, W., Degenaar, P. (2008). A Spatiotemporal Parallel Image Processing on FPGA for Augmented Vision System. In: Sobh, T. (eds) Advances in Computer and Information Sciences and Engineering. Springer, Dordrecht. https://doi.org/10.1007/978-1-4020-8741-7_99
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DOI: https://doi.org/10.1007/978-1-4020-8741-7_99
Publisher Name: Springer, Dordrecht
Print ISBN: 978-1-4020-8740-0
Online ISBN: 978-1-4020-8741-7
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