Skip to main content
SpringerLink
Log in

Composable Multicore Chips

  • Chapter
  • First Online:
Multicore Processors and Systems

Part of the book series: Integrated Circuits and Systems ((ICIR))

  • 1822 Accesses

Abstract

When designing a multicore chip, two primary concerns are how large and powerful to make each core and how many cores to include. A design with a few large cores is attractive for general purpose computing that has coarse-grained threads which depend on instructional-level parallelism for performance. At the other end of the processor granularity spectrum, a large collection of small processors is suited to applications with ample thread-level parallelism. While much of the spectrum between large cores and tiny cores is being pursued by different vendors, each of these fixed architectures are suited only to the range of workloads that maps well to its granularity of parallelism. An alternative is a class of architectures in which the processor granularity (and the number of processors) can be dynamically configured–at runtime. Called composable lightweight processors (CLPs), these architectures consist of arrays of simple processors that can be aggregated together to form larger more powerful processors, depending on the demand of the running application. Experimental results show that matching the granularity of the processors to the granularity of the tasks improves both performance and efficiency over fixed multicore designs.

Portions reprinted, with permission, from “Distributed Microarchitectural Protocols in the TRIPS Prototype Processor,” K. Sankaralingam, R. Nagarajan, R. McDonald, R. Desikan, S. Drolia, M. S. S. Govindan, P. Gratz, D. Gulati, H. Hanson, C. Kim, H. Liu, N. Ranganathan, S. Sethumadhavan, S. Sharif, P. Shivakumar, S. W. Keckler, and D. Burger, International Symposium on Microarchitecture © 2006, IEEE. and “Composable Lightweight Processors,” C. Kim, S. Sethumadhavan, M. Govindan, N. Ranganathan, D. Gulati, D. Burger, and S. W. Keckler, International Symposium on Microarchitecture © 2007, IEEE.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Log in via an institution
Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 129.00
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 169.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info
Hardcover Book
USD 169.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. M. Annavaram, E. Grochowski, and J. P. Shen. Mitigating Amdahl’s law through EPI throttling. In International Symposium on Computer Architecture, pages 298–309, June 2005.

    Google Scholar 

  2. S. Bell, B. Edwards, J. Amann, R. Conlin, K. Joyce, V. Leung, J. MacKay, M. Reif, L. Bao, J. Brown, M. Mattina, C.-C. Miao, C. Ramey, D. Wentzlaff, W. Anderson, E. Berger, N. Fairbanks, D. Khan, F. Montenegro, J. Stickney, and J. Zook. TILE64 processor: A 64-core SoC with mesh interconnect. In International Solid-State Circuits Conference, pages 88–89, Feb 2008.

    Google Scholar 

  3. D. Burger, S. Keckler, K. McKinley, M. Dahlin, L. John, C. Lin, C. Moore, J. Burrill, R. McDonald, and W. Yoder. Scaling to the end of silicon with EDGE architectures. IEEE Computer, 37(7), 2004.

    Google Scholar 

  4. J. Dorsey, S. Searles, M. Ciraula, S. Johnson, N. Bujanos, D. Wu, M. Braganza, S. Meyers, E. Fang, and R. Kumar. An integrated quad-core opteron processor. In International Solid-State Circuits Conference, pages 102–103, Feb 2007.

    Google Scholar 

  5. J. Friedrich, B. McCredie, N. James, B. Huott, B. Curran, E. Fluhr, G. Mittal, E. Chan, Y. Chan, D. Plass, S. Chu, H. Le, L. Clark, J. Ripley, S. Taylor, J. Dilullo, and M. Lanzerotti. Design of the Power6 microprocessor. In International Solid-State Circuits Conference, pages 102–103, Feb 2007.

    Google Scholar 

  6. M. Gebhart, B. Maher, P. Gratz, N. Ranganathan, J. Diamond, B. Robatmili, S. Govindan, S. W. Keckler, D. Burger, and K. McKinley. TRIPS System Evaluation. Technical Report TR-08-31, The University of Texas at Austin, Department of Computer Sciences, Sep 2008.

    Google Scholar 

  7. S. Ghiasi and D. Grunwald. Aide de Camp: Asymmetric Dual Core Design for Power and Energy Reduction. Technical Report CU-CS-964-03, The University of Colorado, Department of Computer Science, 2003.

    Google Scholar 

  8. E. Grochowski, R. Ronen, J. Shen, and H. Wang. Best of both latency and throughput. In International Conference on Computer Design, pages 236–243, Oct 2004.

    Google Scholar 

  9. T. R. Halfhill. Floating point buoys clearspeed. Microprocessor Report, 17(11):19–24, Nov 2003.

    Google Scholar 

  10. T. Ibaraki and N. Katoh. Resource Allocation Problems: Algorithmic Approaches. MIT Press, 1988.

    Google Scholar 

  11. E. Ipek, M. Kirman, N. Kirman, and J. F. Martínez. Core fusion: Accommodating software diversity in chip multiprocessors. In International Symposium on Computer Architecture, pages 186–197, June 2007.

    Google Scholar 

  12. J. A. Kahle, M. N. Day, H. P. Hofstee, C. R. Johns, T. R. Maeurer, and D. Shippy. Introduction to the cell multiprocessor. IBM Journal of Research and Development, 49(4/5), July 2005.

    Google Scholar 

  13. R. Kessler. The Alpha 21264 microprocessor. IEEE Micro, 19(2):24–36, March/April 1999.

    Article  MathSciNet  Google Scholar 

  14. B. Khailany, T. Williams, J. Lin, E. Long, M. Rygh, D. Tovey, and W. J. Dally. A Programmable 512 GOPS stream processor for signal, image, and video processing. In International Solid-State Circuits Conference, pages 272–273, Feb 2007.

    Google Scholar 

  15. C. Kim, D. Burger, and S. W. Keckler. An adaptive, non-uniform cache structure for wire-delay dominated on-chip caches. In International Conference on Architectural Support for Programming Languages and Operating Systems, pages 211–222, Oct 2002.

    Google Scholar 

  16. C. Kim, S. Sethumadhavan, M. Govindan, N. Ranganathan, D. Gulati, D. Burger, and S. W. Keckler. Composable lightweight processors. In International Symposium on Microarchitecture, pages 381–394, Dec 2007.

    Google Scholar 

  17. R. Kumar, K. I. Farkas, N. P. Jouppi, P. Ranganathan, and D. M. Tullsen. Single-ISA heterogeneous multi-core architectures: The potential for processor power reduction. In International Symposium on Microarchitecture, pages 81–92, Dec 2003.

    Google Scholar 

  18. R. Kumar, D. M. Tullsen, P. Ranganathan, N. P. Jouppi, and K. I. Farkas. Single-ISA heterogeneous multi-core architectures for multithreaded workload performance. In International Symposium on Computer Architecture, pages 64–75, June 2004.

    Google Scholar 

  19. F. Latorre, J. González, and A. González. Back-end assignment schemes for clustered multithreaded processors. In International Conference on Supercomputing, pages 316–325, June 2004.

    Google Scholar 

  20. E. Lindholm and S. Oberman. The NVIDIA GeForce 8800 GPU. In Proceedings of the Symposium on High Performance Chips (HotChips-19), August 2007.

    Google Scholar 

  21. B. A. Maher, A. Smith, D. Burger, and K. S. McKinley. Merging head and tail duplication for convergent hyperblock formation. In International Symposium on Microarchitecture, pages 480–491, Dec 2006.

    Google Scholar 

  22. M. R. Marty and M. D. Hill. Virtual hierarchies to support server consolidation. In International Symposium on Computer Architecture, pages 46–56, June 2007.

    Google Scholar 

  23. S. Melvin, M. Shebanow, and Y. Patt. Hardware support for large atomic units in dynamically scheduled machines. In Workshop on Microprogramming and Microarchitecture, pages 60–63, Nov 1988.

    Google Scholar 

  24. U. G. Nawathe, M. Hassan, K. C. Yen, A. Kumar, A. Ramachandran, and D. Greenhill. Implementation of an 8-core, 64-thread, power-efficient SPARC server on a chip. IEEE Journal of Solid-State Circuits, 43(1), Jan 2008.

    Google Scholar 

  25. R. M. Rabbah, I. Bratt, K. Asanović, and A. Agarwal. Versatility and VersaBench: A New Metric and a Benchmark Suite for Flexible Architectures. Technical Report MIT-LCS-TM-646, Massachusetts Institute of Technology, Computer Science and Artificial Intelligence Laboratory, June 2004.

    Google Scholar 

  26. P. Racunas and Y. N. Patt. Partitioned first-level cache design for clustered microarchitectures. In International Conference on Supercomputing, pages 22–31, June 2003.

    Google Scholar 

  27. P. Salverda and C. Zilles. Fundamental performance challenges in horizontal fusion of In-order cores. In International Symposium on High-Performance Computer Architecture, pages 252–263, Feb 2008.

    Google Scholar 

  28. K. Sankaralingam, R. Nagarajan, H. Liu, C. Kim, J. Huh, D. Burger, S. W. Keckler, and C. R. Moore. Exploiting ILP, TLP, and DLP with the polymorphous TRIPS architecture. In International Symposium on Computer Architecture, pages 422–433, June 2003.

    Google Scholar 

  29. K. Sankaralingam, R. Nagarajan, R. McDonald, R. Desikan, S. Drolia, M. S. S. Govindan, P. Gratz, D. Gulati, H. Hanson, C. Kim, H. Liu, N. Ranganathan, S. Sethumadhavan, S. Sharif, P. Shivakumar, S. W. Keckler, and D. Burger. Distributed microarchitectural protocols in the TRIPS prototype processor. In International Symposium on Microarchitecture, pages 480–491, Dec 2006.

    Google Scholar 

  30. S. Sethumadhavan, R. McDonald, R. Desikan, D. Burger, and S. W. Keckler. Design and implementation of the TRIPS primary memory system. In International Conference on Computer Design, pages 470–476, Oct 2006.

    Google Scholar 

  31. S. Sethumadhavan, F. Roesner, J. S. Emer, D. Burger, and S. W. Keckler. Late-binding: Enabling unordered load – store queues. In International Symposium on Computer Architecture, pages 347–357, June 2007.

    Google Scholar 

  32. T. Sherwood, E. Perelman, and B. Calder. Basic block distribution analysis to find periodic behavior and simulation points in applications. In International Conference on Parallel Architectures and Compilation Techniques, pages 3–14, Sep 2001.

    Google Scholar 

  33. A. Smith, J. Burrill, J. Gibson, B. Maher, N. Nethercote, B. Yoder, D. Burger, and K. S. McKinley. Compiling for EDGE architectures. In International Symposium on Code Generation and Optimization, pages 185–195, Mar 2006.

    Google Scholar 

  34. A. Smith, R. Nagarajan, K. Sankaralingam, R. McDonald, D. Burger, S. W. Keckler, and K. S. McKinley. Dataflow predication. In International Symposium on Microarchitecture, pages 89–100, Dec 2006.

    Google Scholar 

  35. A. Snavely and D. M. Tullsen. Symbiotic jobscheduling for a simultaneous multithreaded processor. In International Conference on Architectural Support for Programming Languages and Operating Systems, pages 234–244, Nov 2000.

    Google Scholar 

  36. B. Stackhouse, B. Cherkauer, M. Gowan, P. Gronowski, and C. Lyles. A 65 nm 2-billion-transistor quad-core Itanium processor. In International Solid-State Circuits Conference, pages 92–93, Feb 2008.

    Google Scholar 

  37. D. Tarjan, M. Boyer, and K. Skadron. Federation: Out-of-Order Execution using Simple In-Order Cores. Technical Report CS-2007-11, University of Virginia, Department of Computer Science, Aug 2007.

    Google Scholar 

  38. M. B. Taylor, W. Lee, J. Miller, D. Wentzlaff, I. Bratt, B. Greenwald, H. Hoffmann, P. Johnson, J. Kim, J. Psota, A. Saraf, N. Shnidman, V. Strumpen, M. Frank, S. P. Amarasinghe, and A. Agarwal. Evaluation of the raw microprocessor: An exposed-wire-delay architecture for ILP and streams. In International Symposium on Computer Architecture, pages 2–13, June 2004.

    Google Scholar 

  39. M. Tremblay and S. Chaudhry. A third-generation 65 nm 16-core 32-thread plus 32-scout-thread CMT SPARC Processor. In International Solid-State Circuits Conference, pages 82–83, Feb 2008.

    Google Scholar 

  40. S. Vangal, J. Howard, G. Ruhl, S. Dighe, H. Wilson, J. Tschanz, D. Finan, A. Singh, T. Jacob, S. Jain, C. Roberts, Y. Hoskote, N. Borkar, and S. Borkar. An 80-tile sub-100 W TeraFLOPS processor in 65-nm CMOS. IEEE Journal of Solid-State Circuits, 43(1):29–41, Jan 2008.

    Article  Google Scholar 

  41. E. Waingold, M. Taylor, D. Srikrishna, V. Sarkar, W. Lee, V. Lee, J. Kim, M. Frank, P. Finch, R. Barua, J. Babb, S. Amarasinghe, and A. Agarwal. Baring it all to software: Raw machines. IEEE Computer, 30(9):86–93, 1997.

    Google Scholar 

Download references

Acknowledgments

The authors wish to thank the entire TRIPS hardware team for their contributions to the design and implementation of the TRIPS and TFlex architectures. The team members include: Rajagopalan Desikan, Saurabh Drolia, Mark Gebhart, M.S. Govindan, Paul Gratz, Divya Gulati, Heather Hanson, Changkyu Kim, Haiming Liu, Robert McDonald, Ramadass Nagarajan, Nitya Ranganathan, Karthikeyan Sankaralingam, Simha Sethumadhavan, Sadia Sharif, Premkishore Shivakumar, Stephen W. Keckler, and Doug Burger. The TRIPS project was supported by the Defense Advanced Research Projects Agency under contract F33615-01-C-4106 and by NSF CISE Research Infrastructure grant EIA-0303609.

Author information

Authors and Affiliations

  1. The University of Texas at Austin, 1 University Station C0500, 78712-0233, Austin, TX, USA

    Doug Burger & Stephen W. Keckler

  2. Columbia University, New York, NY, USA

    Simha Sethumadhavan

Authors
  1. Doug Burger
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Stephen W. Keckler
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Simha Sethumadhavan
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Doug Burger .

Editor information

Editors and Affiliations

  1. College of Natural Sciences, University of Texas, Austin, University Station 1, Austin, 78712-0233, U.S.A.

    Stephen W. Keckler

  2. Dept. Electrical Engineering, Stanford University, Stanford, 94305-9510, U.S.A.

    Kunle Olukotun

  3. IBM Software Group, Burnet Rd. 11501, Austin, 78758, U.S.A.

    H. Peter Hofstee

Rights and permissions

Reprints and permissions

Copyright information

© 2009 Springer-Verlag US

About this chapter

Cite this chapter

Burger, D., Keckler, S.W., Sethumadhavan, S. (2009). Composable Multicore Chips. In: Keckler, S., Olukotun, K., Hofstee, H. (eds) Multicore Processors and Systems. Integrated Circuits and Systems. Springer, Boston, MA. https://doi.org/10.1007/978-1-4419-0263-4_3

Download citation

  • DOI: https://doi.org/10.1007/978-1-4419-0263-4_3

  • Published:

  • Publisher Name: Springer, Boston, MA

  • Print ISBN: 978-1-4419-0262-7

  • Online ISBN: 978-1-4419-0263-4

  • eBook Packages: Computer ScienceComputer Science (R0)

Publish with us

Policies and ethics

Search

Navigation