Abstract
Field programmable gate arrays (FPGAs) are examples of complex programmable system-on-chip (PSoC) platforms and comprise dedicated DSP hardware resources and distributed memory. They are ideal platforms for implementing computationally complex DSP systems in image processing and radar, sonar and signal processing. The chapter describes how decidable signal processing graphs are mapped into such platforms and shows how parallelism and pipelining can be controlled from a high level representation to achieve the required speed using minimal hardware resource. The process is demonstrated using a number of simple examples namely a finite impulse response (FIR) filter, lattice filter and a more complex adaptive signal processing design, a least means squares (LMS) filter.
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Woods, R. (2010). Mapping Decidable Signal Processing Graphs into FPGA Implementations. In: Bhattacharyya, S., Deprettere, E., Leupers, R., Takala, J. (eds) Handbook of Signal Processing Systems. Springer, Boston, MA. https://doi.org/10.1007/978-1-4419-6345-1_31
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DOI: https://doi.org/10.1007/978-1-4419-6345-1_31
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