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Power‐Aware Multicore SoC and NoC Design

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Multiprocessor System-on-Chip

Abstract

This chapter examines system-level design of power-efficient systems-on-chip. It starts by examining the sources of power consumption, considering high-level techniques for power-efficient processing, storage and on-chip communication. It also discusses algorithmic- and architecture-driven software transformations and application embedding for power-efficient embedded software. Then, it provides a glimpse at research and development of computer-aided design tools for effective multicore SoC power estimation, analysis and optimization at different abstraction levels and especially system-level modeling, including efforts towards standardization of power formats to enable tool interoperability. Finally, it considers state-of-the-art runtime power management and optimization techniques, including dynamic voltage scaling (DVS), frequency scaling (DFS) and other NoC-based power saving mechanisms. This chapter concludes by briefly outlining future trends towards true system-level power-aware design, providing a large list of references for further study

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References

  1. M. Coppola, M.D. Grammatikakis, R. Locatelli, G. Maruccia, and L. Pieralisi, “Design of cost-efficient interconnect processing units: Spidergon STNoC”, CRC Press, Inc., (2008).

    Google Scholar 

  2. T.Cohen, N. Sriram, D. Leland, Moyer, et al., “Soft Error Considerations for Deep-Submicron CMOS Circuit Applications”, in Proc. IEEE International Electron Device Meeting (IEDM), pp. 315–318, (1999).

    Google Scholar 

  3. H.J. Veendrick, “Short-Circuit Dissipation of Static CMOS Circuitry and its Impact on the Design of Buffer Circuits”, J. Solid-State Circ., SC-19 (4), pp. 468–473, (1984).

    Google Scholar 

  4. T. Burd et. al., “A dynamic voltage scaled Microprocessor System”, in Proc. Int. Solid State Circ. Conf., (2000).

    Google Scholar 

  5. A. Chandrakasan and R. Brodersen, “Low power digital CMOS design”, Kluwer Academic Publisher, (1995).

    Google Scholar 

  6. A. Chatzigeorgiou and G. Stephanides, “Evaluating performance and power of object-oriented vs. procedural programming in embedded processors”, LNCS 2361, J. Blieberger and A. Strohmeier (Eds.), Springer-Verlag, pp. 65–75, (2002).

    Google Scholar 

  7. H. Mehta, R.M. Owens, and M.J. Irwin, “Some issues in Gray code addressing”, in Proc. Great Lakes Symposium on VLSI, pp. 178–180, (1996).

    Google Scholar 

  8. E. Macii, M. Pedram, and F. Somenzi, “High level power modeling, estimation and optimzation”, IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 17, pp. 1061–1079, (1998).

    Article  Google Scholar 

  9. D. Lidsky and J. Rabaey, “Early power exploration: A world wide web application”, in Proc. Design Automation Conf., (1996).

    Google Scholar 

  10. P. Landman, “Low-Power architectural design methodologies”, Ph.D. Dissertation, UC Berkeley, (1994).

    Google Scholar 

  11. P. Landman and J. Rabaey, “Architectural power analysis: The dual bit type method”, IEEE Transactions on VLSI Systems, 3(2), pp. 173-187, (1995).

    Google Scholar 

  12. P. Landman and J. Rabaey, “Activity-sensitive architectural power analysis”, IEEE Trans. on CAD, 15(6), pp. 571–587, (1996).

    Google Scholar 

  13. T. Sato, Y. Ootaguro, M. Nagamatsu, and H. Tago, “Evaluation of architecture-level power estimation for CMOS RISC processors”, in Proc. Symp. Low-Power Electr., pp. 44–45, (1995).

    Google Scholar 

  14. V. Tiwari, S. Malik, and A Wolfe, “Power analysis of embedded software: a first step towards software power minimization”, IEEE Trans. VLSI, 2(4), pp. 437–445, (1994).

    Google Scholar 

  15. WattWatcher Product Sheet, Sente Corp., Chelmsford, MA, (1995).

    Google Scholar 

  16. S. Powell and P. Chau, “Estimating power dissipation of VLSI signal processing chips: The PFA technique”, J. VLSI Signal Proc., Vol. IV, pp. 250–259, (1990).

    Google Scholar 

  17. L. Benini, and G. De Micheli, “System-level power optimization: techniques and tools”, ACM Transactions on Design Automation of Electronic Systems, 5(2), pp. 115–192, (2000).

    Google Scholar 

  18. ACPI,http://www.teleport.com/~acpi/

  19. V. Tiwari, R. Donnelly, S. Malik, and R. Gonzalez, “Dynamic power management for microprocessors: A case study”, VLSI Design, 185–192, (1997).

    Google Scholar 

  20. V. Tiwari, S. Malik, A. Wolfe, and M. Tien-Chien Lee, “Instruction level power analysis and optimization of software,” VLSI Design, 13(2), pp. 223–238, (1996).

    Google Scholar 

  21. M. Caldari, M. Conti, M. Coppola, P. Crippa, et al., “System-level power analysis methodology applied to the AMBA AHB bus”, in Proc. Design Automation and Test in Europe Conf., pp. 32–37, (2003).

    Google Scholar 

  22. T.D. Burd and R.W. Brodersen, “Design issues for dynamic voltage scaling”, in Proc. ISLPED, pp. 9–14, (2000).

    Google Scholar 

  23. C. Kulkarni, F. Catthoor, and H. De Man, “Advanced data layout organization for multimedia applications”, in Proc. IPDPS - Workshop on Parallel, Distributed Computing in Image Processing, Video Processing and Multimedia, (2000).

    Google Scholar 

  24. V. Tiwari, R. Donnelly, S. Malik, and R. Gonzalez, “Dynamic Power Management for Microprocessors: A case study”, VLSI Design, pp. 185–192, (1997).

    Google Scholar 

  25. V. Tiwari, S. Malik, A. Wolfe, and M. T-C. Lee, “Instruction level power analysis and optimization of software”, J. VLSI Signal Proc., 13(2), pp. 223–238, (1996).

    Google Scholar 

  26. V. Tiwari, S. Malik, and A. Wolfe, “Power analysis of embedded software: a first step towards software power minimization”. IEEE Trans. VLSI, 2(4), pp. 437–445, (1994).

    Google Scholar 

  27. Intel PXA27x Processor Family, Electrical, Mechanical, and Thermal Specification, Technical Report, (2005).

    Google Scholar 

  28. M. Farrahi, G. E. Tellez, and M. Sarrafzadeh, “Memory segmentation to exploit sleep mode operation”, in Proc. Design Automation Conf., pp. 36–41, (1995).

    Google Scholar 

  29. F. Catthoor, K. Danckaert, C. Kulkarni, E. Brockmeyer, et al., “Data access and storage management for embedded programmable processors”, Kluwer Acad. Publ., (2002).

    Google Scholar 

  30. H. Zhang and J.M. Rabaey, “Low-swing interconnect interface circuits”, in Proc. Int. Symp. Low Power Electr. and Design, pp. 161–166, (1998).

    Google Scholar 

  31. M. Pedram, and H. Vaishnav, “Power optimization in VLSI layout: A survey”, J. VLSI Signal Processing, 15(3), pp. 221–232, (1997).

    Google Scholar 

  32. L. Xie and P. Qiu, and Q. Qiu, “Partitioned bus coding for energy reduction”, in Proc. Asia South Pacific Design Automation Conf., pp. 1280–1283, (2005).

    Google Scholar 

  33. D.Bertozzi, L. Benini, and G. De Micheli, “Low-Power Error-Resilient Encoding for On-Chip Data Busses”, in Proc. Design Automation and Test in Europe Conf., pp. 102–109, (2002).

    Google Scholar 

  34. J. Walrand, P. Varaiya, High-Performance Communication Networks. Morgan Kaufman, (2000).

    Google Scholar 

  35. I. Papadimitriou, M. Paterakis, “Energy-conserving access protocols for transmitting data in unicast and broadcast mode”, in Proc. Int. Symp. Personal, Indoor and Mobile Radio Communication, pp. 416–420, (2000).

    Google Scholar 

  36. A. Tanenbaum, “Computer networks”. Prentice-Hall, Englewood Cliffs, NJ, (1999).

    Google Scholar 

  37. C. Patel, S. Chai, S. Yalamanchili, D. Shimmel, “Power constrained design of multiprocessor interconnection networks”, IEEE Int. Conf. on Computer Design, pp. 408–416, (1997).

    Google Scholar 

  38. H. Zhang, M. Wan, V. George, J. Rabaey, “Interconnect architecture exploration for low-energy configurable single-chip DSPs”, IEEE Computer Society Workshop on VLSI, pp. 2–8, (1999).

    Google Scholar 

  39. T.T. Ye, L. Benini , and G. De Micheli . “Packetization and routing analysis of on-chip multiprocessor networks”, J. Syst. Arch. - Special Issue on Networks on Chip, 50 (2-3), pp. 81–104, (2004).

    Google Scholar 

  40. P.T. Wolkotte, G. J.M. Smit, N. Kavaldjiev, Jens E. Beckerand J. Becker, “Energy model of networks-on-chip and a bus”,. in Proc. Int. Symp. System-on-Chip, pp. 82–85, (2005).

    Google Scholar 

  41. M.R. Stan and W.P. Burleson, “Low-power encodings for global communication in CMOS VLSI”, IEEE Trans. VLSI Syst., 5, pp. 444–455, (1997).

    Google Scholar 

  42. D. Brooks, V. Tiwari and M. Martonosi, “Wattch: A Framework for Architectural-Level Power Analysis and Optimizations”, in Proc. ProcInt. Symp. Comp. Arch., (2000).

    Google Scholar 

  43. M. Kandemir, N. Vijaykrishnan, M. Irwin, and W. Ye, “Influence of compiler optimizations on system power”, in Proc. 37th Design Automation Conf., (2000).

    Google Scholar 

  44. J. Hu and R. Marculescu. “Exploiting the routing flexibility for energy/performance aware mapping of regular NoC architectures”, in Proc. Design, Automation and Test in Europe Conf., (2003).

    Google Scholar 

  45. J. Hu and R. Marculescu. “Energy-aware communication and task scheduling for network-on-chip architectures under real-time constraints”, in Proc. Design, Automation and Test in Europe Conf., (2004).

    Google Scholar 

  46. J. Hu and R. Marculescu. “Energy- and performance-aware mapping for regular noc architectures”. IEEE Trans. Computer-Aided Design of Integr. Circ. and Syst., 24(4), pp. 551–562, (2005).

    Google Scholar 

  47. S. Murali and G. De Micheli. “Bandwidth-constrained mapping of cores onto NoC architectures”, in Proc. Design, Automation and Test in Europe Conf., (2004).

    Google Scholar 

  48. S. Murali and G. De Micheli. “SUNMAP: a tool for automatic topology selection and generation for NoCs”, in Proc. Design Automation Conf., (2004).

    Google Scholar 

  49. L. Bononi, N. Concer, and M. Grammatikakis, “System-level tools for NoC-based multicore design” in Embedded Multicore Architectures. Ed. G. Kornaros, Chapter 6, CRC Press, Taylor and Francis Group, (2009).

    Google Scholar 

  50. C. Marcon, N. Calazans, F. Moraes, and A. Susin. “Exploring NoC mapping strategies: an energy and timing aware technique”, in Proc. Design, Automation and Test in Europe, (2005).

    Google Scholar 

  51. S. Rosinger, K. Schroder, and W. Nebel, “Power management aware low leakage behavioural synthesis”, Int. Conf. Digital Syst. Design, pp. 149–156, (2009).

    Google Scholar 

  52. ChipVision, “Orinoco: A high-level power estimation and optimization tool suite”, see http://www.chipvision.com

  53. Synopsys Innovator, Datasheet. Available from http://www.synopsys.com/virtualplatform

  54. X. Liu and M.C. Papaefthymiou, “HyPE: hybrid power estimation for ip-based programmable systems”, in Proc. Asia and South Pacific Design Automation Conf., pp. 606–609, (2003).

    Google Scholar 

  55. A. Sinha and A.Chandrakasan, “JouleTrack – A web-based tool for software energy profiling”, in Proc. Design Automation Conf., pp. 220–225, (2001).

    Google Scholar 

  56. E. Senn, J. Laurent, N. Julien, and E. Martin, “Softexplorer: estimating and optimizing the power and energy consumption of a C program for DSP applications”, EURASIP J. Appl. Signal Proc., Vol 1, pp. 2641–2654, (2005).

    Google Scholar 

  57. T. Simunic, L. Benini, and G. D. Micheli, “Cycle-accurate simulation of energy consumption in embedded systems”, in Proc. Design Automation Conf., pp. 867–872, (1999).

    Google Scholar 

  58. J. Henkel and Y. Li, “Avalanche: an environment for design space exploration and optimization of low-power embedded systems”, Transactions on VLSI Systems, 10, pp. 454–468, (2002).

    Google Scholar 

  59. T. M. Lajolo, A. Raghunathan, S. Dey, and L. Lavagno, “Efficient power co-estimation techniques for system-on- chip design,” in Proc. Design Automation and Test in Europe Conf., (2000).

    Google Scholar 

  60. BullDast, Powerchecker: An integrated environment for rtl power estimation and optimization”, Version 4.0, available from http://www.bulldast.com

  61. PowerChecker by BullDAST, see http://www.bulldast.com/powerchecker.html.

  62. Bluespec, see http://bluespec.com

  63. F. Klein, G. Araujo, R. Azevedo, R. Leao, et al., “PowerSC: An efficient framework for high-level power exploration”, in Proc. Midwest Symp. Circ. and Syst., pp. 1046–1049, (2007)

    Google Scholar 

  64. L. Pieralisi, M. Caldari, G.B. Vece, M. Conti, et al., “Power-Kernel: Power analysis methodology and library in SystemC”, in Proc. VLSI Circ. and Syst., Vol. II, (2005).

    Google Scholar 

  65. M. Caldari, M. Conti, M. Coppola, P. Crippa, et al. “System-level power analysis methodology applied to the AMBA AHB Bus”, in Proc. Design Automation and Test in Europe Conf., (2003).

    Google Scholar 

  66. S. Xanthos, A. Chatzigeorgiou, and G. Stephanides, “Energy estimation with systemC: A programmer's perspective”, in Proc. WSEAS Int. Conf. on Systems, Computational Methods in Circuits and Systems Applications, pp.1–6, (2003).

    Google Scholar 

  67. IEEE P1801, available from http://ieeexplore.ieee.org

  68. L. Benini, A. Bogliolo, and G. D. Micheli, “A survey of design techniques for system-level dynamic power management”, IEEE Trans. VLSI, 8(3), pp. 299–316, (2000).

    Google Scholar 

  69. ITRS, 2009, http://www.itrs.net

  70. The European Design Automation Roadmap, available from http://www.medeaplus.org

  71. P. Hofstee. “Power efficient processor architecture and the Cell processor, in Proc. HPCA-11, (2005).

    Google Scholar 

  72. P. Kongetira, K. Aingaran, and K. Olukotun, “A 32-way multithreaded SPARC processor”, IEEE Micro, 25, pp. 21–29, (2005).

    Google Scholar 

  73. W. Dally and B. Towles, “Route packets, not wires: on-chip interconnection networks”, in Proc. Design Automation Conf., (2001).

    Google Scholar 

  74. R. Ho, K. Mai, and M. Horowitz, “The future of wires”, in Proc. IEEE, 89(4), (2001).

    Google Scholar 

  75. N. Magen, A. Kolodny, U. Weiser, and N. Shamir, “Interconnect power dissipation in a microprocessor”, in Proc. System Level Interconnect Prediction, (2004).

    Google Scholar 

  76. Y. Hu, Y. Zhu, H. Chen, R. Graham, and C.-K Cheng, “Communication latency aware low power NoC synthesis”, in Proc. Design Automation Conf., pp. 574–579, (2006).

    Google Scholar 

  77. V. Soteriou and L.-S. Peh, “Exploring the design space of self-regulating power-aware on/off interconnection networks”, IEEE Trans. Parallel Distrib. Syst., 18(3), 393–408, (2007).

    Google Scholar 

  78. X. Chen and L.-S. Peh, “Leakage power modeling and optimization in interconnection networks”, in Proc. Symp. Low Power Electr. and Design, (2003).

    Google Scholar 

  79. P.-P. Sotiriadis and A. Chandrakasan, “Bus energy minimization by transition pattern coding (TPC) in deep submicron technologies”, in Proc. Int. Conf., pp. 322–327, (2000).

    Google Scholar 

  80. T. Lv, J. Henkel, H. Lekatsas, and W. Wolf, “A dictionary-based en/decoding scheme for low-power data buses”, IEEE Trans. VLSI Syst., 11 (5), pp. 943–951, (2003).

    Google Scholar 

  81. M.R. Stan and W.P. Burleson, “Bus-invert coding for low power I/O”, IEEE Trans. VLSI Syst., 3 (1), pp. 49–58, (1995).

    Google Scholar 

  82. V. Wen, M. Whitney, Y. Patel, and J. Kubiatowicz, “Exploiting prediction to reduce power on buses.”, in Proc. Symp. High Proc. Comp. Arch., pp. 2–13, (2004).

    Google Scholar 

  83. K. Lee, S.-J. Lee, and H.-J. You, “SILENT: serialized low energy transmission coding for on-chip interconnection networks”, in Proc. Int. Conf. CAD, pp. 448–451, (2004).

    Google Scholar 

  84. G. Kornaros, “Temporal coding schemes for energy efficient data transmission in Systems-on-Chip”, in Proc. Workshop Intelligent Solutions in Embedded Systems, pp. 111–118, (2009).

    Google Scholar 

  85. D. Ernst, N.S. Kim, S. Das, S. Pant, et al., “A low-power pipeline based on circuit-level timing speculation”, in Proc. Int. Symp. Micro-architecture, pp. 7–18, (2003).

    Google Scholar 

  86. A. Drake, R. Senger, H. Deogun, G. Carpenter, et al., “A distributed critical-path timing monitor for a 65nm high-performance microprocessor ”, in Proc. Solid-State Circuits Conf., (2007).

    Google Scholar 

  87. R. McGowen, C. A. Poirier, C. Bostak, J. Ignowski, et al., “Power and Temperature Control on a 90nm Itanium Family Processor”, IEEE Journal on Solid State circuits, 41 (1), pp. 229–237, (2006).

    Google Scholar 

  88. P. Royannez, et. al., “90nm low leakage SoC design techniques for wireless applications”, in Proc. Solid State Circuits Conf., (2005).

    Google Scholar 

  89. C. Qikai, M. Meterelliyoz, and K. Roy, “A CMOS thermal sensor and its applications in temperature adaptive design”, in Proc. Int. Symp. Quality Electronic Design, (2006).

    Google Scholar 

  90. S. Remarsu and S. Kundu, “On process variation tolerant low cost thermal sensor design in 32nm CMOS technology”, in Proc. Great Lakes symposium on VLSI, pp. 487–492, (2009).

    Google Scholar 

  91. T. Wolf, S. Mao, D. Kumar, B. Datta, W. Burleson, and G. Gogniat, “Collaborative monitors for embedded system security”, in Proc. Workshop on Embedded Syst. Security, (2006).

    Google Scholar 

  92. C Isci, G Contreras, and M Martonosi, “Live, runtime phase monitoring and prediction on real systems with application to dynamic power management”, in Proc. Int. Symposium on Microarchitecture, (2006).

    Google Scholar 

  93. L.F. Leung and C.Y. Tsui, “Energy-aware synthesis of networks-on-chip implemented with voltage islands”, in Proc. Design Automation Conf., pp. 128–131, (2007).

    Google Scholar 

  94. U.Y. Ogras, R. Marculescu, P. Choudhary, and D. Marculescu, “Voltage-frequency island partitioning for gals-based networks-on-chip”, in Proc Design Automation Conf., pp. 110–115, (2007).

    Google Scholar 

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Acknowledgements

Work of the first author towards this project has been indirectly funded by ISD S.A. and in particular, EU sources: a) ARTEMIS/SCALOPES “SCAlable LOw Power Embedded platformS” Joint Undertaking under grant agreement n¯ 100029 (duration: 2009–2010), and b) ENIAC MODERN “MOdeling and DEsign of Reliable, process variation-aware Nanoelectronic devices, circuits and systems” under reference n¯ ENIAC-120003 MODERN (duration 2009–2011), and corresponding Greek funding authorities.

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  1. ST Microelectronics, J. Horowitz 12, 38019, Grenoble, France

    Marcello Coppola

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  1. Miltos D. Grammatikakis
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  2. George Kornaros
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  3. Marcello Coppola
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Correspondence to Marcello Coppola .

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  1. Fak. Elektrotechnik, Inst. Technik der, Universität Karlsruhe, Engesser Str. 5, Karlsruhe, 76128, Germany

    Michael Hübner

  2. Institut für Technik der, Informationsverarbeitung, Karlsruhe Institute of Technology (KIT), Vincenz-Prießnitz-Straße 1, Karlsruhe, 76131, Germany

    Jürgen Becker

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Grammatikakis, M.D., Kornaros, G., Coppola, M. (2011). Power‐Aware Multicore SoC and NoC Design. In: Hübner, M., Becker, J. (eds) Multiprocessor System-on-Chip. Springer, New York, NY. https://doi.org/10.1007/978-1-4419-6460-1_8

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