Skip to main content
SpringerLink
Log in

Variation and Aging Tolerance in FPGAs

  • Chapter
  • First Online:
Low-Power Variation-Tolerant Design in Nanometer Silicon

Abstract

Parameter variation and component aging are becoming a significant problems for all digital circuits including FPGAs. These effects degrade performance, increase power dissipation, and cause permanent faults at manufacturing time and during the lifetime of an FPGA . Several techniques have been developed to tolerate variation and aging in ASICs; FPGA designers have been quick to adopt and customize these strategies. While FPGAs can use many ASIC techniques verbatim, they have a distinct advantage to aid in the development of more innovate solutions: reconfigurability. Reconfigurability gives us the ability to spread wear effects over the chip which is not possible in ASICs. This chapter examines the impact of variation and wear on FPGAs and notes the benefit that can be gained from variation and aging tolerance techniques that operate open-loop.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Log in via an institution
Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 84.99
Price excludes VAT (USA)
  • Available as EPUB and PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 139.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info
Hardcover Book
USD 109.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

References

  1. Achronix Semiconductor Corporation, Inc. (2010) Achronix Speedster Data Sheet, preliminary (v1.0) edn http://www.achronix.com/

  2. Katsuki K, Kotani M, Kobayashi K, Onodera H (2005) A yield and speed enhancement scheme under within-die variations on 90 nm LUT array. In: Proceedings of the IEEE custom integrated circuits conference, pp 601–604

    Google Scholar 

  3. Kumar A, Anis M (2010) FPGA design for timing yield under process variations. IEEE Trans VLSI Syst 18(3):423–435

    Article  Google Scholar 

  4. Lin Y, He L, Hutton M (2008) Stochastic physical synthesis considering prerouting interconnect uncertainty and process variation for FPGAs. IEEE Trans VLSI Syst 16(2):124

    Article  Google Scholar 

  5. Lucas G, Dong C, Chen D (2010) Variation-aware placement for FPGAs with multi-cycle statistical timing analysis. In: Proceedings of the international symposium on field-programmable gate arrays. ACM, New York, NY, pp 177–180

    Google Scholar 

  6. Manohar R (2006) Reconfigurable asynchronous logic. In: Proceedings of the IEEE custom integrated circuits conference, pp 13–20

    Google Scholar 

  7. Martin A, Nystrom M (2006) Asynchronous techniques for system-on-chip design. Proc IEEE 94(6):1089–1120

    Article  Google Scholar 

  8. Paul S, Mukhopadhyay S, Bhunia S (2009) A variation-aware preferential design approach for memory based reconfigurable computing. In: Proceedings of the international conference on computer-aided design. ACM, New York, NY, pp 180–183

    Google Scholar 

  9. Ramakrishnan K, Suresh S, Vijaykrishnan N, Irwin M (2007) Impact of NBTI on FPGAs. In: Proceedings of the international conference on VLSI design. IEEE Computer Society, pp 717–722

    Google Scholar 

  10. Sedcole P, Cheung PYK (2006) Within-die delay variability in 90 nm FPGAs and beyond. In: Proceedings of the international conference on field-programmable technology, pp 97–104

    Google Scholar 

  11. Sivaswamy S, Bazargan K (2008) Statistical analysis and process variation-aware routing and skew assignment for FPGAs. Trans Reconfig Technol Syst 1(1):1–35. doi: http://doi.acm.org/10.1145/1331897.1331900

    Article  Google Scholar 

  12. Srinivasan S, Mangalagiri P, Xie Y, Vijaykrishnan N, Sarpatwari K (2006) FLAW: FPGA lifetime awareness. In: Proceedings of the ACM/IEEE design automation conference. ACM, p 635

    Google Scholar 

  13. Stott EA, Wong JSJ, Pete Sedcole P, Cheung PYK (2010) Degradation in FPGAs: measurement and modelling. In: Proceedings of the international symposium on field-programmable gate arrays. ACM Press, New York, NY, p 229

    Google Scholar 

  14. Tsu W, Macy K, Joshi A, Huang R, Walker N, Tung T, Rowhani O, George V, Wawrzynek J, DeHon A (1999) HSRA: high-speed, hierarchical synchronous reconfigurable array. In: Proceedings of the international symposium on field-programmable gate arrays, pp 125–134

    Google Scholar 

  15. Wong C, Martin A, Thomas P (2003) An architecture for asynchronous FPGAs. In: Proceedings of the international conference on field-programmable technology, pp 170–177

    Google Scholar 

  16. Wong H, Cheng L, Lin Y, He L (2005) FPGA device and architecture evaluation considering process variations. In: Proceedings of the international conference on computer-aided design. IEEE Computer Society, p. 24

    Google Scholar 

  17. Wong JSJ, Sedcole P, Cheung PYK (2008) A transition probability based delay measurement method for arbitrary circuits on FPGAs. In: Proceedings of the international conference on field-programmable technology, pp 105–112

    Google Scholar 

  18. Wong JSJ, Sedcole P, Cheung PYK (2009) Self-measurement of combinatorial circuit delays in FPGAs. Trans Reconfig Technol Syst 2(2):1–22

    Article  Google Scholar 

Download references

Author information

Authors and Affiliations

  1. Department of Computer Science, California Institute of Technology, Pasadena, CA, USA

    Nikil Mehta

  2. Department of Electrical and Systems Engineering, University of Pennsylvania, Philadelphia, PA, USA

    André DeHon

Authors
  1. Nikil Mehta
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. André DeHon
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Nikil Mehta .

Editor information

Editors and Affiliations

  1. Dept. Electrical Engineering &, Computer Science, Case Western Reserve University, Euclid Avenue 10900, Cleveland, 44106-7071, Ohio, USA

    Swarup Bhunia

  2. School of Electrical &, Computer Engineering, Georgia Institute of Technology, Ferst Drive 266, Atlanta, 30332-0250, Georgia, USA

    Saibal Mukhopadhyay

Rights and permissions

Reprints and permissions

Copyright information

© 2011 Springer Science+Business Media, LLC

About this chapter

Cite this chapter

Mehta, N., DeHon, A. (2011). Variation and Aging Tolerance in FPGAs. In: Bhunia, S., Mukhopadhyay, S. (eds) Low-Power Variation-Tolerant Design in Nanometer Silicon. Springer, Boston, MA. https://doi.org/10.1007/978-1-4419-7418-1_11

Download citation

  • DOI: https://doi.org/10.1007/978-1-4419-7418-1_11

  • Published:

  • Publisher Name: Springer, Boston, MA

  • Print ISBN: 978-1-4419-7417-4

  • Online ISBN: 978-1-4419-7418-1

  • eBook Packages: EngineeringEngineering (R0)

Publish with us

Policies and ethics

Search

Navigation