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The Promises and Limitations of 3-D Integration

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3D Integration for NoC-based SoC Architectures

Part of the book series: Integrated Circuits and Systems ((ICIR))

Abstract

The intrinsic computational efficiency (ICE) of silicon defines the upper limit of the amount of computation within a given technology and power envelope. The effective computational efficiency (ECE) and the effective computational density (ECD) of silicon, by taking computation, memory and communication into account, offer a more realistic upper bound for computation of a given technology. Among other factors, they consider how distributed the memory is, how much area is occupied by computation, memory and interconnect, and the geometric properties of 3-D stacked technology with through silicon vias (TSV) as vertical links. We use ECE and ECD to study the limits of performance under different memory distribution constraints of various 2-D and 3-D topologies, in current and future technology nodes. Among other results, our model shows that in a 35 nm technology a 16 stack 3-D system can, as a theoretical upper limit, obtain 3.4 times the performance of a 2-D system (8.8 Tera OPS vs 2.6 TOPS) at 70% reduced frequency (2.1 vs 3.7 GHz) on 1/8 the total area (50 vs 400 mm2).

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Notes

  1. 1.

    Again, this is a simplification, because there are fewer operators but they are pipelined. In effect, 8 operations can be completed per cycle in the best case, motivating the number 8 that we use in this example.

  2. 2.

    This figure depends less on architectural choices, but more on how information is coded, protected and compressed. Although a simplification, it is important to note that the same assumption is used for all architectures and the relative comparisons and main trends are not sensitive to the chosen value for switching activity.

  3. 3.

    We assume registers and small register files close to the operators. Reading and writing of registers is not considered as memory access.

References

  1. T. Claasen. High speed: Not the only way to exploit the intrinsic computational power of silicon. Proceedings of the International Solid State Circuits Conference (ISSCC), 1999.

    Google Scholar 

  2. Tilera Corporation. Tilera Home Page. http://www.tilera.com.

  3. W.J. Dally. Performance analysis of k-ary n-cube interconnection networks. IEEE Transactions on Computers, 39(6):775–785, 1990.

    Article  MathSciNet  Google Scholar 

  4. A.Y. Weldezion, M. Grange, D. Pamunuwa, Z. Lu, A. Jantsch, R. Weerasekera and H. Tenhunen. Scalability of network-on-chip communication architecture for 3-D meshes. Proceedings of the International Symposium on Networks-on-Chip, 2009.

    Google Scholar 

  5. V.F. Pavlidis and E.G. Friedman. 3-D topologies for networks-on-chip. IEEE Transactions on Very Large Scale Integration Systems, 15(10):1081, 2007.

    Article  Google Scholar 

  6. R. Weerasekera, D. Pamunuwa, L.-R. Zheng and H. Tenhunen. Two-dimensional and three-dimensional integration of heterogeneous electronic systems under cost, performance and technological constraints. IEEE Transactions on Computer-Aided Design, 28(8):1237–1250, 2009.

    Article  Google Scholar 

  7. B. Feero and P.P. Pande. Networks on chip in a three dimensional environment: A performance evaluation. IEEE Transactions on Computers, 58(1), 2009.

    Article  MathSciNet  Google Scholar 

  8. F. Li, C. Nicopoulos, T. Richardson, Y. Xie, V. Narayanan and M. Kandemir. Design and management of 3 D chip multiprocessors using network-in-memory. ACM SIGARCH Computer Architecture News, 34(2):130–141, 2006.

    Article  Google Scholar 

  9. G. Loh. 3D-stacked memory architectures for multi-core processors. Proceedings for the 35th ACM/IEEE International Symposium on Computer Architecture (ISCA), 2008.

    Google Scholar 

  10. S. Lai and T. Lowrey. OUM—A 180 nm nonvolatile memory cell element technology for stand alone and embedded applications. Proceedings of the International Electronics Device Meeting, 2001.

    Google Scholar 

  11. J. Janzen. The micron system-power calculator. Micron web site, 2009. http://www.micron.com/support/dram/power_calc.html

  12. S. Bell, B. Edwards, J. Amann, R. Conlin, K. Joyce, V. Leung, J. MacKay, M. Reif, L. Bao, J. Brown, M. Mattina, C.-C. Miao, C. Ramey, D. Wentzlaff, W. Anderson, E. Berger, N. Fairbanks, D. Khan, F. Montenegro, J. Stickney and J. Zook. TILE64TM Processor: A 64-Core SoC with mesh interconnect. Proceedings of the International Solid State Circuits Conference, 2008.

    Google Scholar 

  13. R. Ho, K.W. Mai and M.A. Horowitz. The future of wires. Proceedings of the IEEE, 89(4):490–504, 2001.

    Article  Google Scholar 

  14. R. Weerasekera, M. Grange, D. Pamunuwa, H. Tenhunen and L.-R. Zheng. Compact modelling of through-silicon vias (TSVs) in three-dimensional (3-D) integrated circuits. Proceedings IEEE International Conference on 3D System Integration (3D IC), 2009.

    Google Scholar 

  15. S. Perri, P. Corsonello and G. Staino. A low-power sub-nanosecond standard-cells based adder. Proceedings of the 2003 10th IEEE International Conference on Electronics, Circuits and Systems, 2003.

    Google Scholar 

  16. W.J. Dally, U.J. Kapasi, B. Khailany, J.H. Ahn and A. Das. Stream processors: progammability and efficiency. Queue, 2(1):52–62, 2004.

    Article  Google Scholar 

  17. U. Nawathe, M. Hassan, K. Yen, L. Warriner, B. Upputuri, D. Greenhill, A. Kumar and H. Park. An 8-Core 64-Thread 64b Power-Efficient SPARC SoC. Proceedings of the Inetrnational Solid State Circuits Conference, 2007.

    Google Scholar 

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Correspondence to Axel Jantsch .

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Jantsch, A., Grange, M., Pamunuwa, D. (2011). The Promises and Limitations of 3-D Integration. In: Sheibanyrad, A., Pétrot, F., Jantsch, A. (eds) 3D Integration for NoC-based SoC Architectures. Integrated Circuits and Systems. Springer, New York, NY. https://doi.org/10.1007/978-1-4419-7618-5_2

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  • DOI: https://doi.org/10.1007/978-1-4419-7618-5_2

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  • Publisher Name: Springer, New York, NY

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  • Online ISBN: 978-1-4419-7618-5

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