Skip to main content
SpringerLink
Log in

Testing 3D Stacked ICs Containing Through-Silicon Vias

  • Chapter
  • First Online:
3D Integration for NoC-based SoC Architectures

Part of the book series: Integrated Circuits and Systems ((ICIR))

Abstract

To meet customer’s product-quality expectations, each individual IC needs to be tested for manufacturing defects incurred during its many high-precision, and hence defect-prone manufacturing steps; these tests should be both effective and cost-efficient. The semiconductor industry is preparing itself now for three-dimensional stacked ICs (3D-SICs) based on Through-Silicon Vias (TSVs), which, due to their many compelling benefits, are quickly gaining ground. Test solutions need to be ready for this new generation of ‘super chips’. 3D-SICs are chips where all basic, as well as most advanced test technologies come together. In addition, they pose some truly new test challenges with respect to complexity and cost, due to their advanced manufacturing processes and physical access limitations. This chapter focuses on the challenges of testing 3D-SICs, and describes for which challenges solutions are already available or emerging. It provides an overview of the manufacturing steps of TSV-based 3D-SICs, as far as relevant for testing. Subsequently, it discusses flows for wafer-level and package-level tests, the challenges with respect to test contents and wafer-level probe access, and the on-chip Design-for-Test (DfT) infrastructure required for 3D-SICs.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Log in via an institution
Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 89.00
Price excludes VAT (USA)
  • Available as EPUB and PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 119.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info
Hardcover Book
USD 169.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

References

  1. Robert S. Patti. Three-Dimensional Integrated Circuits and the Future of System-on-Chip Designs. Proceedings of the IEEE, 94(6):1214–1224, 2006.

    Article  Google Scholar 

  2. Eric Beyne and Bart Swinnen. 3D System Integration Technologies. Proceedings of IEEE International Conference on Integrated Circuit Design and Technology (ICICDT), pages 1–3, 2007.

    Google Scholar 

  3. Philip Garrou, Christopher Bower and Peter Ramm, Eds. Handbook of 3D Integration—Technology and Applications of 3D Integrated Circuits. Wiley-VCH, Weinheim, Germany, 2008.

    Google Scholar 

  4. Gabriel H. Loh, Yuan Xie and Bryan Black. Processor Design in 3D Die-Stacking Technologies. IEEE Micro, 27(3):31–48, 2007.

    Article  Google Scholar 

  5. Roshan Weerasekera, Li-Rong Zheng, Dinesh Pamanuwa and Hannu Tenhunen. Extending Systems-on-Chip to the Third Dimension: Performance, Cost and Technological Tradeoffs. Proceedings International Conference on Computer-Aided Design (ICCAD), pages 212–219, 2007.

    Google Scholar 

  6. James W. Joyner and James D. Meindl. Opportunities for Reduced Power Dissipation Using Three-Dimensional Integration. Proceedings IEEE International Interconnect Technology Conference (IITC), pages 148–150, 2002.

    Google Scholar 

  7. Bart Swinnen. 3D Technologies: Requiring More Than 3 Dimensions from Concept to Product. Proceedings IEEE International Interconnect Technology Conference (IITC), pages 59–62, 2009.

    Google Scholar 

  8. Eric Beyne et al. Through-Silicon Via and Die Stacking Technologies for Micro Systems Integration. Proceedings IEEE International Electron Devices Meeting (IEDM), pages 1–4, 2008.

    Google Scholar 

  9. Kaustav Banerjee et al. 3-D ICs: A Novel Chip Design for Improving Deep-Submicrometer Interconnect Performance and Systems-on-Chip Integration. Proceedings of the IEEE, 89(5):602–633, 2001.

    Article  Google Scholar 

  10. Shamik Das, Anantha Chandrakasan and Rafael Reif. Three-Dimensional Integrated Circuits: Performance, Design Methodology, and CAD Tools. Proceedings of IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pages 13–18, 2003.

    Google Scholar 

  11. Shamik Das, Anantha Chandrakasan and Rafael Reif. Design Tools for 3-D Integrated Circuits. Proceedings IEEE Asia South Pacific Design Automation Conference (ASP-DAC), pages 53–56, 2003.

    Google Scholar 

  12. Uksong Kang et al. 8 Gb 3D DDR3 DRAM Using Through-Silicon-Via Technology. Proceedings International Solid State Circuits Conference (ISSCC), pages 130–132, 2009.

    Google Scholar 

  13. Christianto C. Liu et al. Bridging the Processor-Memory Performance Gap with 3D IC Technology. IEEE Design & Test of Computers, 22(6):556–564, 2005.

    Article  Google Scholar 

  14. Bryan Black et al. 3D Processing Technology and its Impact on iA32 Microprocessors. Proceedings International Conference on Computer Design (ICCD), pages 316–318, 2004.

    Google Scholar 

  15. Bart Swinnen et al. 3D Integration by Cu–Cu Thermo-Compression Bonding of Extremely Thinned Bulk-Si Die Containing 10 μm Pitch Through-Si Vias. Proceedings IEEE International Electron Devices Meeting (IEDM), pages 1–4, 2006.

    Google Scholar 

  16. Jan Van Olmen et al. 3D Stacked IC Demonstration using a Through Silicon Via First Approach. Proceedings IEEE International Electron Devices Meeting (IEDM), pages 1–4, 2008.

    Google Scholar 

  17. Anne Jourdain et al. Electrically Yielding Collective Hybrid Bonding for 3D Stacking of ICs. Electronic Components and Technology Conference (ECTC), pages 11–13, 2009.

    Google Scholar 

  18. Rafael Reif et al. Fabrication Technologies for Three-Dimensional Integrated Circuits. Proceedings International Symposium on Quality of Electronic Design (ISQED), pages 33–37, 2002.

    Google Scholar 

  19. John U. Knickerbocker et al. 3D Silicon Integration. Electronic Components and Technology Conference (ECTC), pages 538–543, 2008.

    Google Scholar 

  20. Bioh Kim et al. Factors Affecting Copper Filling Process Within High Aspect Ratio Deep Vias for 3D Chip Stacking. Electronic Components and Technology Conference (ECTC), pages 1–6, 2006.

    Google Scholar 

  21. Twan Bearda et al. Post-Dicing Particle Control for 3D Stacked IC Integration Flows. Electronic Components and Technology Conference (ECTC), pages 1513–1516, 2009.

    Google Scholar 

  22. Yervant Zorian, Ed. Multi-Chip Module Test Strategies. Kluwer Academic Publishers, 1997.

    Google Scholar 

  23. Erik J. Marinissen and Yervant Zorian. Testing 3D Chips Containing Through-Silicon Vias. Proceedings IEEE International Test Conference (ITC), 2009.

    Google Scholar 

  24. Greg Smith et al. Yield Considerations in the Choice of 3D Technology. Proceedings International Symposium on Semiconductor Manufacturing (ISSM), pages 1–3, 2007.

    Google Scholar 

  25. Sherief Reda, Gregory Smith and Larry Smith. Maximizing the Functional Yield of Wafer-to-Wafer 3-D Integration. IEEE Transactions on VLSI Systems, 17:1357–1362, 2009.

    Article  Google Scholar 

  26. Jouke Verbree et al. On the Cost-Effectiveness of Matching Repositories of Pre-Tested Wafers for Wafer-to-Wafer 3D Chip Stacking. Proceedings IEEE European Test Symposium (ETS), pages 36–41, 2010.

    Google Scholar 

  27. Michael Bushnell and Vishwani Agrawal. Essentials of Electronic Testing for Digital, Memory & Mixed-Signal VLSI Circuits. Wiley-VCH, Weinheim, Germany, 2000.

    Google Scholar 

  28. Dirk K. de Vries. Investigation of Gross Die Per Wafer Formulas. IEEE Transactions on Semiconductor Manufacturing, 18(1):136–139, 2005.

    Article  Google Scholar 

  29. Yervant Zorian, Erik J. Marinissen and Sujit Dey. Testing Embedded-Core Based System Chips. Proceedings IEEE International Test Conference (ITC), pages 130–143, 1998.

    Google Scholar 

  30. Ozgur Sinanoglu et al. Test Data Volume Comparison: Monolithic vs. Modular SoC Testing. IEEE Design & Test of Computers, 26(3):25–37, 2009.

    Google Scholar 

  31. Rohit Kapur. CTL for Test Information of Digital ICs. Kluwer Academic Publishers, 2003.

    Google Scholar 

  32. Francisco da Silva, Teresa McLaurin and Tom Waayers. The Core Test Wrapper Handbook: Rationale and Application of IEEE Std. 1500. Springer, Berlin, Germany, 2006.

    Google Scholar 

  33. Sandeep K. Goel and Erik J. Marinissen. SOC Test Architecture Design for Efficient Utilization of Test Bandwidth. ACM Transactions on Design Automation of Electronic Systems, 8(4):399–429, 2003.

    Google Scholar 

  34. Erik J. Marinissen. The Role of Test Protocols in Automated Test Generation for Embedded-Core-Based System ICs. Journal of Electronic Testing: Theory and Applications, 18(4/5):435–454, 2002.

    Article  Google Scholar 

  35. Akihiro Ikeda et al. Design and Measurements of Test Element Group Wafer Thinned to 10 μm for 3D System in Package. Proceedings IEEE International Conference on Microelectronic Test Structures, pages 161–164, 2004.

    Google Scholar 

  36. Dan Perry et al. Impact of Thinning and Packaging on a Deep Sub-Micron CMOS Product. Electronic Workshop Digest of DATE 2009 Friday Workshop on 3D Integration, page 282, 2009. (http://www.date-conference.com/files/file/09-workshops/date09-3dws-digestv2-090504.pdf).

    Google Scholar 

  37. Menglin Tsai et al. Through Silicon Via (TSV) Defect/Pinhole Self Test Circuit for 3D-IC. Proceedings IEEE International Conference on 3D System Integration (3DIC), pages 1–8, 2009.

    Google Scholar 

  38. Po-Yuan Chen, Cheng-Wen Wu and Ding-Ming Kwai. On-Chip TSV Testing for 3D IC Before Bonding Using Sense Amplification. Proceedings IEEE Asian Test Symposium (ATS), pages 450–455, 2009.

    Google Scholar 

  39. Erik J. Marinissen et al. Minimizing Pattern Count for Interconnect Test under a Ground Bounce Constraint. IEEE Design & Test of Computers, 20(2):8–18, 2003.

    Article  Google Scholar 

  40. William H. Kautz. Testing of Faults in Wiring Networks. IEEE Transactions on Computers, C-23(4):358–363, 1974.

    Article  Google Scholar 

  41. P. Goel and M.T. McMahon. Electronic Chip-in-Place Test. Proceedings IEEE International Test Conference (ITC),, pages 83–90, 1982.

    Google Scholar 

  42. Paul T. Wagner. Interconnect Testing with Boundary Scan. Proceedings IEEE International Test Conference (ITC), pages 52–57, 1987.

    Google Scholar 

  43. William R. Mann et al. The Leading Edge of Production Wafer Probe Test Technology. Proceedings IEEE International Test Conference (ITC), pages 1168–1195, 2004.

    Google Scholar 

  44. Gil-Su Kim, Makoto Takamiya and Takayasu Sakurai. A Capacitive Coupling Interface with High Sensitivity for Wireless Wafer Testing. Proceedings IEEE International Conference on 3D System Integration (3DIC), pages 1–5, 2009.

    Google Scholar 

  45. Brian Moore et al. High Throughput Non-Contact SIP Testing. Proceedings IEEE International Test Conference (ITC), 2007. Paper 12.3.

    Google Scholar 

  46. Erik Jan Marinissen et al. Contactless Testing: Possibility or Pipe-Dream? Proceedings Design, Automation, and Test in Europe (DATE), pages 676–671, 2009.

    Google Scholar 

  47. Dimitrios Velenis et al. Impact of 3D Design Choices on Manufacturing Cost. Proceedings IEEE International Conference on 3D System Integration (3DIC), pages 1–5, 2009.

    Google Scholar 

  48. Janusz Rajski et al. Embedded Deterministic Test. IEEE Transactions on Computer-Aided Design (TCAD), 23(5):776–792, 2004.

    Article  Google Scholar 

  49. Xiaoxia Wu, Paul Falkenstern and Yuan Xie. Scan Chain Design for Three-dimensional Integrated Circuits (3D ICs). Proceedings International Conference on Computer Design (ICCD), pages 208–214, 2007.

    Google Scholar 

  50. Xiaoxia Wu et al. Test-Access Mechanism Optimization for Core-Based Three-Dimensional SOCs. Proceedings International Conference on Computer Design (ICCD), pages 212–218, 2008.

    Google Scholar 

  51. Xiaoxia Wu et al. Test-Access Solutions for Three-Dimensional SOCs. Proceedings IEEE International Test Conference (ITC), page 1, October 2008.

    Google Scholar 

  52. Li Jiang, Lin Huang and Qiang Xu. Test Architecture Design and Optimization for Three-Dimensional SoCs. Proceedings Design, Automation, and Test in Europe (DATE), pages 220–225, 2009.

    Google Scholar 

  53. Harald Vranken et al. Enhanced Reduced Pin-Count Test for Full-Scan Design. Proceedings IEEE International Test Conference (ITC), pages 738–747, 2001.

    Google Scholar 

  54. Yervant Zorian. A Structured Testability Approach for Multi-Chip Modules Based on BIST and Boundary-Scan. IEEE Transactions on Components, Packaging and Manufacturing Technology—Part B, 17(3):283–290, 1994.

    Article  Google Scholar 

  55. Yervant Zorian and Hakim Bederr. An Effective Multi-Chip BIST Scheme. Journal of Electronic Testing: Theory and Applications, 10(1–2):87–95, 1997.

    Google Scholar 

Download references

Acknowledgments

We thank many colleagues at IMEC for stimulating discussions, especially Eric Beyne, Ingrid De Wolf, Luc Dupas, Mario Gonzalez, Anne Jourdain, Paresh Limaye, Pol Marchal, Nikolaos Minas, Dan Perry, Philippe Roussel, Geert Van der Plas, Bart Swinnen, Kris Vanstreels, Dimitrios Velenis, and Jouke Verbree.

Author information

Authors and Affiliations

  1. IMEC, Kapeldreef 75, 3001, Leuven, Belgium

    Erik Jan Marinissen

Authors
  1. Erik Jan Marinissen
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Erik Jan Marinissen .

Editor information

Editors and Affiliations

  1. TIMA Laboratory, 46, Avenue Felix Viallet, Grenoble, 38000, France

    Abbas Sheibanyrad

  2. TIMA Laboratory, Avenue Felix Viallet 46, Grenoble, 38000, France

    Frédéric Pétrot

  3. Royal Institute of Technology, Forum 120, Kista, SE-16440, Sweden

    Axel Jantsch

Rights and permissions

Reprints and permissions

Copyright information

© 2011 Springer Science+Business Media, LLC

About this chapter

Cite this chapter

Marinissen, E. (2011). Testing 3D Stacked ICs Containing Through-Silicon Vias. In: Sheibanyrad, A., Pétrot, F., Jantsch, A. (eds) 3D Integration for NoC-based SoC Architectures. Integrated Circuits and Systems. Springer, New York, NY. https://doi.org/10.1007/978-1-4419-7618-5_3

Download citation

  • DOI: https://doi.org/10.1007/978-1-4419-7618-5_3

  • Published:

  • Publisher Name: Springer, New York, NY

  • Print ISBN: 978-1-4419-7617-8

  • Online ISBN: 978-1-4419-7618-5

  • eBook Packages: EngineeringEngineering (R0)

Publish with us

Policies and ethics

Search

Navigation