Abstract
Our concern is the design of provably correct asynchronous circuits. In such circuits there may occur hazards, due to the delay of signals along wires and components. Informally, a hazard is a time interval during which the output of a circuit, or circuit component, is wrong. Hazards are hardly ever defined formally in the literature. For a synchronous circuit designer this might be no problem as he assumes the outputs of all components are correct (and stabile) by the next clock edge. Asynchronous or clockless circuits may feature hazards, even though all components are correct. So it is of vital importance for the asynchronous system designer to be able to reason formally about hazards. We shall design an algebra, a formal system, for this purpose and we shall use it to design asynchronous finite-state machines. For reasons of space most of the proofs have been omitted. These will be included in an expanded version of this paper.
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References
E.B. Eichelberger. Hazard detection in combinational and sequential switching circuits. IBM Journal of Research and Development, 9: 90–99, March 1965.
Guiseppe Fantauzzi. An algebraic model for the analysis of logical circuits. IEEE Transactions on Computers, 23 (6), June 1974.
C.A.R. Hoare. A couple of novelties in the propositional calculus. In C.A.R. Hoare and C.B. Jones, editors, Essays in Computing Science, chapter 19, pages 325–331. Prentice Hall, 1989.
Simon L Peyton Jones. A practical technique for designing asynchronous finite-state machines. Technical report, Glasgow university, 1991.
Mark B. Josephs. Algebraic verification of speed-independent circuits. Technical Report PRG-TR-18–91, Programming Research Group, Oxford University Computing Laboratory, 1991.
D.W. Lewis. Hazard detection by quinary simulation of logic devices with bounded propagation delays. Master’s thesis, Syracuse University, New York, January 1972.
Carver Mead and Lynn Conway. Introduction to VLSI Systems. Addison-Wesley, 1980.
Charles L. Seitz. System Timing, chapter 7, pages 218–262. in: [7].
B. Thompson. A five-valued transitional logic. November 1992.
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© 1993 British Computer Society
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Meijer, E. (1993). Hazard Algebra and the Design of Asynchronous Automata. In: Launchbury, J., Sansom, P. (eds) Functional Programming, Glasgow 1992. Workshops in Computing. Springer, London. https://doi.org/10.1007/978-1-4471-3215-8_15
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DOI: https://doi.org/10.1007/978-1-4471-3215-8_15
Publisher Name: Springer, London
Print ISBN: 978-3-540-19820-8
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