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Systems for Late Code Modification

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Code Generation — Concepts, Tools, Techniques

Part of the book series: Workshops in Computing ((WORKSHOPS COMP.))

Abstract

Modifying code after the compiler has generated it can be useful for both optimization and instrumentation. Several years ago we designed the Mahler system, which uses link-time code modification for a variety of tools on our experimental Titan workstations. Killian’s Pixie tool works even later, translating a fully-linked MIPS executable file into a new version with instrumentation added. Recently we wanted to develop a hybrid of the two, that would let us experiment with both optimization and instrumentation on a standard workstation, preferably without requiring us to modify the normal compilers and linker. This paper describes prototypes of two hybrid systems, closely related to Mahler and Pixie. We implemented basic-block counting in both, and compare the resulting time and space expansion to those of Mahler and Pixie.

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References

  1. Borg A, Kessler RE, Lazana G, Wall DW. Long address traces from RISC machines: Generation and analysis. In Seventeenth Annual International Symposium on Computer Architecture, pp 270–279. IEEE Computer Society Press, 1990.

    Google Scholar 

  2. Chow F, Himelstein M, Killian E, Weber L. Engineering a RISC compiler system. In Digest of Papers: Compcon 86, pp 132–137. IEEE Computer Society Press, 1986.

    Google Scholar 

  3. Chow FC. Minimizing register usage penalty at procedure calls. In Proceedings of the SIGPLAN ‘88 Conference on Programming Language Design and Implementation, pp 85–94, 1988.

    Google Scholar 

  4. Davidson JW, Fraser CW. Code selection through object code optimization. Transactions on Programming Languages and Systems, 6 (4): 505–526, 1984.

    Article  Google Scholar 

  5. Davidson JW, Fraser CW. Register allocation and exhaustive peephole optimization. Software-Practice and Experience, 14 (9): 857–865, 1984.

    Article  Google Scholar 

  6. Gibbons PB, Muchnick SS. Efficient instruction scheduling for a pipelined architecture. In Proceedings of the SIGPLAN ‘86 Symposium on Compiler Construction, pp 11–16, 1986.

    Google Scholar 

  7. Goldberg A, Hennessy J. MTOOL: A method for detecting memory bottlenecks. Technical Report TN-17, Digital Equipment Corp., 250 University Ave., Palo Alto, California, 1990.

    Google Scholar 

  8. Graham SL, Kessler PB, McKusick MK. An execution profiler for modular programs. Software-Practice and Experience, 13 (8): 120–126, 1983.

    Article  Google Scholar 

  9. Hennessy J, Gross T. Postpass code optimization of pipeline constraints. ACM Transactions on Programming Languages and Systems, 5(3):422–448,1983.

    Article  MATH  Google Scholar 

  10. Himelstein MI, Chow FC, Enderby K. Cross-module optimizations: Its implementation and benefits. In Proceedings of the Summer 1987 USENIX Conference, pp 347–356. The USENIX Association, 1987.

    Google Scholar 

  11. Johnson SC. Postloading for fun and profit. In Proceedings of the Winter 1990 USENIX Conference, pp 325–330. The USENIX Association, 1990.

    Google Scholar 

  12. Jouppi NP, Dion J, Boggs D, Nielsen MJK. Multititan: Four architecture papers. Technical Report 87/8, Digital Equipment Corp., 250 University Ave., Palo Alto, California, 1988.

    Google Scholar 

  13. Kane G. MIPS R2000 Risc Architecture. Prentice Hall, 1987.

    Google Scholar 

  14. Killian EA. Personal communication.

    Google Scholar 

  15. McFarling S. Program optimization for instruction caches. In Third International Symposium on Architectural Support for Programming Languages and Operating Systems, pp 183–191, 1989.

    Google Scholar 

  16. McKeeman WM. Peephole optimization. Communications of the ACM, 8 (7): 443–444, 1965.

    Article  Google Scholar 

  17. MIPS Computer Systems. RISCompiler and C Programmer’s Guide. MIPS Computer Systems, Inc., 930 Arques Ave., Sunnyvale, California 94086, 1986.

    Google Scholar 

  18. Nielsen MJK. Titan system manual. Technical Report 86/1, Digital Equipment Corp., 250 University Ave., Palo Alto, California, 1986.

    Google Scholar 

  19. Santhanam V, Odnert D. Register allocation across procedure and module boundaries. In Proceedings of the SIGPLAN ‘80 Conference on Programming Language Design and Implementation, pp 28–39, 1990.

    Google Scholar 

  20. Steenkiste PA, Hennessy JL. A simple interprocedural register allocation algorithm and its effectiveness for LISP. ACM Transactions on Programming Languages and Systems, 11 (1): 1–32, 1989.

    Article  Google Scholar 

  21. Wall DW. Global register allocation at link-time. In Proceedings of the SIGPLAN ‘86 Symposium on Compiler Construction, pp 264–275, 1986.

    Google Scholar 

  22. Wall DW. Register windows vs. register allocation. In Proceedings of the SIGPLAN ‘88 Conference on Programming Language Design and Implementation, pp 67–78, 1988.

    Google Scholar 

  23. Wall DW. Link-time code modification. Technical Report 89/17, Digital Equipment Corp., 250 University Ave., Palo Alto, California, 1989.

    Google Scholar 

  24. Wall DW. Experience with a software-defined machine architecture. ACM Transactions on Programming Languages and Systems, to appear. Also available as WRL Research Report 91/10, Digital Equipment Corp., 250 University Ave., Palo Alto, California. August 1991.

    Google Scholar 

  25. Wall DW, Powell ML. The Mahler experience: Using an intermediate language as the machine description. In Second International Symposium on Architectural Support for Programming Languages and Operating Systems, pp 100–104, 1987.

    Google Scholar 

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© 1992 Springer-Verlag London

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Wall, D.W. (1992). Systems for Late Code Modification. In: Giegerich, R., Graham, S.L. (eds) Code Generation — Concepts, Tools, Techniques. Workshops in Computing. Springer, London. https://doi.org/10.1007/978-1-4471-3501-2_15

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  • DOI: https://doi.org/10.1007/978-1-4471-3501-2_15

  • Publisher Name: Springer, London

  • Print ISBN: 978-3-540-19757-7

  • Online ISBN: 978-1-4471-3501-2

  • eBook Packages: Springer Book Archive

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