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Code Generation — Concepts, Tools, Techniques pp 146–170Cite as

Phase Ordering of Register Allocation and Instruction Scheduling

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Part of the book series: Workshops in Computing ((WORKSHOPS COMP.))

Abstract

Register allocation and instruction scheduling are often separated due to the complexity of each. But if register allocation is performed before scheduling, it may introduce artificial data precedence, keeping the instruction scheduler from doing its best job. On the other hand, waiting until after scheduling to perform register allocation may produce impossible schedules. In this paper we present a unified approach to instruction scheduling and global (beyond basic blocks) register allocation.

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Author information

Authors and Affiliations

  1. Hewlett-Packard Laboratories, Palo Alto, Calif., USA

    Stefan M. Freudenberger

  2. Silicon Graphics, Milford, Conn., USA

    John C. Ruttenberg

Authors
  1. Stefan M. Freudenberger
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  2. John C. Ruttenberg
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Editor information

Editors and Affiliations

  1. Arbeitsgruppe Praktische Informatik, Technische Fakultät, Universität Bielefeld, Postfach 10 01 31, 4800, Bielefeld 1, Germany

    Robert Giegerich (Dr) (Dr)

  2. Computer Science Division — EECS, University of California, Berkeley, 571 Evans Hall, 94720, Berkeley, CA, USA

    Susan L. Graham PhD

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© 1992 Springer-Verlag London

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Cite this paper

Freudenberger, S.M., Ruttenberg, J.C. (1992). Phase Ordering of Register Allocation and Instruction Scheduling. In: Giegerich, R., Graham, S.L. (eds) Code Generation — Concepts, Tools, Techniques. Workshops in Computing. Springer, London. https://doi.org/10.1007/978-1-4471-3501-2_9

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  • DOI: https://doi.org/10.1007/978-1-4471-3501-2_9

  • Publisher Name: Springer, London

  • Print ISBN: 978-3-540-19757-7

  • Online ISBN: 978-1-4471-3501-2

  • eBook Packages: Springer Book Archive

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