Abstract
Unification is one of the most important processes in Prolog systems. In this paper, We propose a dedicated hardware unifier consisting of four stages of pipelined processors, which find variable bindings known as ‘mgu’. To achieve pipelining, terms are expressed especially by a sequence of symbols with their arities. To enhance its performance, only terms which are bound by variables are managed within this unifier, and the structure sharing method is also adopted to prevent the occurrence of redundancy of variables. Moreover ‘occur-check’, which is known to be a heavy load on software systems, is easily performed during unification.
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© 1988 Kluwer Academic Publishers, Boston
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Tanabe, M., Aiso, H. (1988). The Unification Processor by Pipeline Method. In: Kitsuregawa, M., Tanaka, H. (eds) Database Machines and Knowledge Base Machines. The Kluwer International Series in Engineering and Computer Science, vol 43. Springer, Boston, MA. https://doi.org/10.1007/978-1-4613-1679-4_45
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DOI: https://doi.org/10.1007/978-1-4613-1679-4_45
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