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Application Specific Instruction Set DSP Processors

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Handbook of Signal Processing Systems

Abstract

In this chapter, application specific instruction set processors (ASIP) for DSP applications will be introduced and discussed for readers who want general information about ASIP technology. The introduction includes ASIP design flow, source code profiling, architecture exploration, assembly instruction set design, design of assembly language programming toolchain, firmware design, benchmarking, and microarchitecture design. Special challenges from designing multicore ASIP are discussed. Two examples, design for instruction set level acceleration of radio baseband, and design for instruction set level acceleration of image and video signal processing, are introduced.

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References

  1. D. Liu, Embedded DSP Processor Design, Application Specific Instruction Set Processors, Elsevier 2008 ISBN 9780123741233

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  2. D. Liu, A Nilsson, D Wu, J Eilert, and E Tell, Bridging dream and reality: Programmable baseband processor for software-defined radio, IEEE Communication Magazine, pp 134–140, September 2009

    Google Scholar 

  3. Coresonic Inc., http://www.coresonic.com/

  4. P. Karlstrom, D. Liu, NoGAP a Micro Architecture Construction Framework, SAMOS IX: International Symposium on Systems, Architectures, MOdeling and Simulation, July 2009.

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  5. David Salomon, Data Compression, The Complete Reference, 3rd Ed., Springer, ISBN: 9781846286025, 2006.

    Google Scholar 

  6. Berkeley Design Technology, Inc., http://www.bdti.com

  7. Embedded Microprocessor Benchmarking Consortium, http://www.eembc.org

  8. M. Hohenauer, H. Scharwaechter, K. Karuri, O. Wahlen, T. Kogel, R. Leupers, G. Ascheid, H. Meyr, G. Braun, Compiler-in-loop Architecture Exploration for Efficient Application Specific Embedded Processor Design, magazine, Design and Elektronik. WEKA, Verlag 2004.

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  9. D. Liu, et al, ePUMA, Embedded Parallel DSP Processor with Unique Memory Access, ICICS 2011, Singapore.

    Google Scholar 

  10. IBM, Cell Broadband Engine Programming Handbook, Version 1.11, May.2008.

    Google Scholar 

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Correspondence to Dake Liu .

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Liu, D., Wang, J. (2013). Application Specific Instruction Set DSP Processors. In: Bhattacharyya, S., Deprettere, E., Leupers, R., Takala, J. (eds) Handbook of Signal Processing Systems. Springer, New York, NY. https://doi.org/10.1007/978-1-4614-6859-2_21

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  • DOI: https://doi.org/10.1007/978-1-4614-6859-2_21

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  • Publisher Name: Springer, New York, NY

  • Print ISBN: 978-1-4614-6858-5

  • Online ISBN: 978-1-4614-6859-2

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