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Design and performance Evaluation of a Fault-Tolerant, Hard-Real-Time, Parallel Processor

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Responsive Computer Systems: Steps Toward Fault-Tolerant Real-Time Systems

Abstract

The continuing integration of computer systems into critical control applications requires that the systems tolerate any hardware fault which may occur during operations. Additionally, the control stability aspects of these applications require that data operations (such as input, processing, and output) be performed within some bounded real-time constraints. Any missed time deadlines can be viewed as system failures, with results as consequential as hardware failures. Thus contemporary designs must consider both the hardware fault tolerance as well as the deterministic scheduling of real-time tasks.

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References

  1. Abler, T., A Network Element Based Fault Tolerant Processor, MS Thesis, Massachusetts Institute of Technology, Cambridge, MA, May 1988.

    Google Scholar 

  2. Babikyan, C., “The Fault Tolerant Parallel Processor Operating System Concepts and Performance Measurement Overview,” Proceedings of the 9th Digital Avionics Systems Conference, October 1990, pp. 366–371.

    Google Scholar 

  3. Carlow, G. D., “Architecture of the Space Shuttle Primary Avionics Software System”, Communications of the ACM, 27(9):926–36, September 1984.

    Article  Google Scholar 

  4. Clasen, R. J., System Performance Modeling and Analysis of a Fault-Tolerant Real-Time Parallel Processor MS Thesis, Northeastern University, Boston, MA, May 1993.

    Google Scholar 

  5. Di Vito, B. L., Butler, R. W., Caldwell, J. L., “Formal Design and Verification of a Reliable Computing Platform for Real-Time Control,” NASA Technical Memorandum 102716, October 1990.

    Google Scholar 

  6. Hanaway, J. F., Morrehead, R. W., Space Shuttle Avionics System, NASA SP-504, 1989.

    Google Scholar 

  7. Harper, R., Critical Issues in Ultra-Reliable Parallel Processing, PhD Thesis, Massachusetts Institute of Technology, Cambridge, MA, June 1987.

    Google Scholar 

  8. Harper, R., Lala, J., Deyst, J., “Fault Tolerant Parallel Processor Overview,” 18th International Symposium on Fault-Tolerant Computing, June 1988, pp. 252–257.

    Google Scholar 

  9. Harper, R., “Reliability Analysis of Parallel Processing Systems,” Proceedings of the 8th Digital Avionics Systems Conference., October 1988, pp. 213–219.

    Google Scholar 

  10. Harper, R., Lala, J., Fault Tolerant Parallel Processor, J. Guidance, Control, and Dynamics, V. 14, N. 3, May-June 1991, pp. 554–563.

    Google Scholar 

  11. Kopetz, H., et al., “Distributed Fault-Tolerant Real-Time Systems: The MARS Approach,” IEEE Micro, 9(1):25–40, February 1989.

    Article  Google Scholar 

  12. Lehr, T., et al., “Visualizing Performance Debugging,” Computer, October 1989, pp. 38–51.

    Google Scholar 

  13. Liu, C. L., Layland, J. W., “Scheduling Algorithms for Multiprograming in a hard Real-time Environment,” J. ACM, 20(1):46–61, 1973.

    Article  MathSciNet  MATH  Google Scholar 

  14. Lamport, L., Shostak, R., Pease, M., “The Byzantine Generals Problem,” ACM Transactions on Programming Languages and Systems, Vol. 4, No. 3, July 1982, p. 382–401.

    Article  MATH  Google Scholar 

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© 1995 Springer Science+Business Media New York

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Clasen, R., Harper, R., Czeck, E. (1995). Design and performance Evaluation of a Fault-Tolerant, Hard-Real-Time, Parallel Processor. In: Fussell, D.S., Malek, M. (eds) Responsive Computer Systems: Steps Toward Fault-Tolerant Real-Time Systems. The Springer International Series in Engineering and Computer Science, vol 297. Springer, Boston, MA. https://doi.org/10.1007/978-1-4615-2271-3_12

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  • DOI: https://doi.org/10.1007/978-1-4615-2271-3_12

  • Publisher Name: Springer, Boston, MA

  • Print ISBN: 978-0-7923-9563-8

  • Online ISBN: 978-1-4615-2271-3

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