Abstract
Numerical processing is at the core of applications in many areas ranging from scientific and engineering calculations to financial computing. These applications are usually executed on large servers or supercomputers to exploit their high speed, high level of parallelism and high bandwidth to memory.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Similar content being viewed by others
Notes
- 1.
Shifting (\(2^i\)) is done by hard-wiring the AND-2 array’s output bits.
References
S. Borkar, “Electronics beyond nano-scale CMOS,” Proc. of the 43rd ACM/IEEE Design Automation Conference, pp. 807–808, 2006.
D. K. Schroder and J. A. Babcock, “Negative bias temperature instability: Road to cross in deep submicron silicon semiconductor manufacturing,” Journal of Applied Physics, vol. 94, no. 1, pp. 1–18, July 2003.
X. Fan, W.-D. Weber, and L. A. Barroso, “Power Provisioning for a Warehouse-sized Computer,” Proc. of ACM International Symposium on Computer Architecture, June 2007.
M. Cornea, “Precision, Accuracy, and Rounding Error Propagation in Exascale Computing,” Proc. of 21st IEEE Symposium on Computer Arithmetic, pp. 231–234, Apr. 2013.
IEEE Standard for Floating-Point Arithmetic, IEEE Computer Society Std. 754, 2008.
M. D. Ercegovac and T. Lang, Digital Arithmetic. Morgan Kaufmann Publishers, 2004.
S. Oberman, G. Favor, and F. Weber, “AMD 3DNow! technology: architecture and implementations,” IEEE Micro, vol. 19, no. 2, pp. 37–48, Mar./Apr. 1999.
T. Lang and J. Bruguera, “Floating-point multiply-add-fused with reduced latency,” IEEE Transactions on Computers, vol. 53, no. 8, pp. 988–1003, Aug. 2004.
M. D. Ercegovac and T. Lang, Division and Square Root: Digit Recurrence Algorithms and Implementations. Kluwer Academic Publisher, 1994.
H. Baliga, N. Cooray, E. Gamsaragan, P. Smith, K. Yoon, J. Abel, and A. Valles, “Improvements in the Intel Core2 Penryn Processor Family Architecture and Microarchitecture,” Intel Technology Journal, pp. 179–192, Oct. 2008.
N. Burgess and C. Hinds, “Design issues in radix-4 SRT square root and divide unit,” Conference Record of 35th Asilomar Conference on Signals, Systems and Computers, vol. 2, pp. 1646–1650, 2001.
G. Gerwig, H. Wetter, E. Schwarz, and J. Haess, “High performance floating-point unit with 116 bit wide divider,” Proc. of 16th IEEE Symposium on Computer Arithmetic, pp. 87–94, Jun. 2003.
A. Nannarelli and T. Lang, “Low-power division: comparison among implementations of radix 4, 8 and 16,” Proc. of 14th IEEE Symposium on Computer Arithmetic, pp. 60–67, 1999.
S. Oberman, “Floating point division and square root algorithms and implementation in the AMD-K7 microprocessor,” Proc. of 14th IEEE Symposium on Computer Arithmetic, pp. 106–115, 1999.
NVIDIA. “Fermi. NVIDIA’s Next Generation CUDA Compute Architecture”. Whitepaper. [Online]. Available: http://www.nvidia.com/content/PDF/fermi_white_papers/ NVIDIA_Fermi_Compute_Architecture_Whitepaper.pdf
D. DasSarma and D. Matula, “Measuring the accuracy of ROM reciprocal tables,” IEEE Transactions on Computers, vol. 43, no. 8, pp. 932–940, Aug. 1994.
D. A. Patterson and J. L. Hennessy, Computer Organization and Design-the hardware/software interface, 4th ed.Morgan Kaufmann Publishers Inc., 2009.
S. Oberman and M. Flynn, “Design issues in division and other floating-point operations,” IEEE Transactions on Computers, vol. 46, no. 2, pp. 154–161, Feb. 1997.
W. Liu, A. Calimera, A. Nannarelli, E. Macii, and M. Poncino, “On-chip Thermal Modeling Based on SPICE Simulation,” Proc. of 19th International Workshop on Power And Timing Modeling, Optimization and Simulation (PATMOS 2009), pp. 66–75, Sept. 2009.
T. Sato, J. Ichimiya, N. Ono, K. Hachiya, and M. Hashimoto, “On-chip thermal gradient analysis and temperature flattening for SoC design,” Proc. of the 2005 Asia and South Pacific Design Automation Conference (ASP-DAC), vol. 2, pp. 1074–1077, Jan. 2005.
A. Nannarelli, “FPGA Based Acceleration of Decimal Operations,” in Proc. of International Conference on ReConFigurable Computing and FPGA’s, Dec. 2011, pp. 146–151.
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2015 Springer Science+Business Media New York
About this chapter
Cite this chapter
Liu, W., Nannarelli, A. (2015). Power and Thermal Efficient Numerical Processing. In: Khan, S., Zomaya, A. (eds) Handbook on Data Centers. Springer, New York, NY. https://doi.org/10.1007/978-1-4939-2092-1_8
Download citation
DOI: https://doi.org/10.1007/978-1-4939-2092-1_8
Published:
Publisher Name: Springer, New York, NY
Print ISBN: 978-1-4939-2091-4
Online ISBN: 978-1-4939-2092-1
eBook Packages: Computer ScienceComputer Science (R0)