Years and Authors of Summarized Original Work
2002; Sundararajan, Sapatnekar, Parhi
Problem Definition
For a detailed exposition of the solution approach presented in this entry, please refer to [15]. As evidenced by the successive announcement of ever-faster computer systems in the past decade, increasing the speed of VLSI systems continues to be one of the major requirements for VLSI system designers today. Faster integrated circuits are making possible newer applications that were traditionally considered difficult to implement in hardware. In this scenario of increasing circuit complexity, reduction of circuit delay in integrated circuits is an important design objective. Transistor sizing is one such task that has been employed for speeding up circuits for quite some time now [6]. Given the circuit topology, the delay of a combinational circuit can be controlled by varying the sizes of transistors in the circuit. Here, the size of a transistor is measured in terms of its channel...
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Recommended Reading
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Sundararajan, V. (2016). Gate Sizing. In: Kao, MY. (eds) Encyclopedia of Algorithms. Springer, New York, NY. https://doi.org/10.1007/978-1-4939-2864-4_159
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