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Symbolic Model Checking

  • Reference work entry
  • First Online:
Encyclopedia of Algorithms
  • 162 Accesses

Years and Authors of Summarized Original Work

  • 1990; Burch, Clarke, McMillan, Dill

Problem Definition

Design verification is the process of taking a design and checking that it works correctly. More specifically, every design verification paradigm has three components [6]: (1) a language for specifying the design in an unambiguous way, (2) a language for specifying properties that are to be checked of the design, and (3) a checking procedure, which determines whether the properties hold off the design.

The verification problem is very general: it arises in low-level designs, e.g., checking that a combinational circuit correctly implements arithmetic, as well as high-level designs, e.g., checking that a library written in high-level language correctly implements an abstract data type.

Hardware Verification

The verification of hardware designs is particularly challenging. Verification is difficult in part because the large number of concurrent operations make it very difficult to conceive...

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Recommended Reading

  1. Biere A, Cimatti A, Clarke E, Fujita M, Zhu Y (1999) Symbolic model checking using sat procedures instead of BDDs. In: ACM design automation conference, New Orleans

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  6. Gupta A (1993) Formal hardware verification methods: a survey. Form Method Syst Des 1:151–238

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  8. Katz R (1993) Contemporary logic design. Benjamin/Cummings Publishing Company, Redwood City

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  14. Touati H, Savoj H, Lin B, Brayton RK, Sangiovanni-Vincentelli AL (1990) Implicit state enumeration of finite state machines using BDDs. In: IEEE international conference on computer-aided design, Santa Clara, pp 130–133, Nov 1990

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Correspondence to Adnan Aziz .

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Aziz, A., Prakash, A. (2016). Symbolic Model Checking. In: Kao, MY. (eds) Encyclopedia of Algorithms. Springer, New York, NY. https://doi.org/10.1007/978-1-4939-2864-4_416

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