Years and Authors of Summarized Original Work
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1990; Burch, Clarke, McMillan, Dill
Problem Definition
Design verification is the process of taking a design and checking that it works correctly. More specifically, every design verification paradigm has three components [6]: (1) a language for specifying the design in an unambiguous way, (2) a language for specifying properties that are to be checked of the design, and (3) a checking procedure, which determines whether the properties hold off the design.
The verification problem is very general: it arises in low-level designs, e.g., checking that a combinational circuit correctly implements arithmetic, as well as high-level designs, e.g., checking that a library written in high-level language correctly implements an abstract data type.
Hardware Verification
The verification of hardware designs is particularly challenging. Verification is difficult in part because the large number of concurrent operations make it very difficult to conceive...
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Recommended Reading
Biere A, Cimatti A, Clarke E, Fujita M, Zhu Y (1999) Symbolic model checking using sat procedures instead of BDDs. In: ACM design automation conference, New Orleans
Bryant R (1986) Graph-based algorithms for Boolean function manipulation. IEEE Trans Comput C-35:677–691
Burch JR, Clarke EM, McMillan KL, Dill DL (1992) Symbolic model checking: 1020 states and beyond. Inf Comput 98(2):142–170
Cormen TH, Leiserson CE, Rivest RH, Stein C (2001) Introduction to algorithms. MIT, Cambridge
Emerson EA (1990) Temporal and modal logic. In: van Leeuwen J (ed) Formal models and semantics. Volume B of handbook of theoretical computer science. Elsevier Science, Amsterdam, pp 996–1072
Gupta A (1993) Formal hardware verification methods: a survey. Form Method Syst Des 1:151–238
Jackson D (2006) Software abstractions: logic, language, and analysis. MIT, Cambridge
Katz R (1993) Contemporary logic design. Benjamin/Cummings Publishing Company, Redwood City
McMillan KL (1993) Symbolic model checking. Kluwer Academic, Boston
Mony H, Baumgartner J, Paruthi V, Kanzelman R, Kuehlmann A (2004) Scalable automated verification via expert-system guided transformations. In: Formal methods in CAD, Austin
Ranjan R, Aziz A, Brayton R, Plessier B, Pixley C (1995) Efficient BDD algorithms for FSM synthesis and verification. In: Proceedings of the international workshop on logic synthesis, Tahoe City, May 1995
Savoj H (1992) Don’t cares in multi-level network optimization. Ph.D. thesis, Electronics Research Laboratory, College of Engineering, University of California, Berkeley
Shiple TR, Hojati R, Sangiovanni-Vincentelli AL, Brayton RK (1994) Heuristic minimization of BDDs using don’t cares. In: ACM design automation conference, San Diego, June 1994
Touati H, Savoj H, Lin B, Brayton RK, Sangiovanni-Vincentelli AL (1990) Implicit state enumeration of finite state machines using BDDs. In: IEEE international conference on computer-aided design, Santa Clara, pp 130–133, Nov 1990
Wile B, Goss J, Roesner W (2005) Comprehensive functional verification. Morgan-Kaufmann
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Aziz, A., Prakash, A. (2016). Symbolic Model Checking. In: Kao, MY. (eds) Encyclopedia of Algorithms. Springer, New York, NY. https://doi.org/10.1007/978-1-4939-2864-4_416
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