Years and Authors of Summarized Original Work
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1999; Chu, Wong
Problem Definition
The problem is about minimizing the delay of an interconnect wire in a very-large-scale integration (VLSI) circuit by changing the width (i.e., sizing) of the wire. The delay of interconnect wire has become a dominant factor in determining VLSI circuit performance for advanced VLSI technology. Wire sizing has been shown to be an effective technique to minimize the interconnect delay. The work of Chu and Wong [1] shows that the wire sizing problem can be transformed into a convex quadratic program. This quadratic programming approach is very efficient and can be naturally extended to simultaneously consider buffer insertion, which is another popular interconnect delay minimization technique. Previous approaches apply either a dynamic programming approach [2], which is computationally more expensive, or an iterative greedy approach [3, 4], which is hard to combine with buffer insertion.
The wire sizing...
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Recommended Reading
Chu CCN, Wong DF (1999) A quadratic programming approach to simultaneous buffer insertion/sizing and wire sizing. IEEE Trans Comput-Aided Des 18(6):787–798
Lillis J, Cheng C-K, Lin T-T (1995) Optimal and efficient buffer insertion and wire sizing. In: Proceedings of the custom integrated circuits conference, Santa Clara, pp 259–262
Cong J, Leung K-S (1995) Optimal wiresizing under the distributed Elmore delay model. IEEE Trans Comput-Aided Des 14(3):321–336
Chen C-P, Wong DF (1996) A fast algorithm for optimal wire-sizing under Elmore delay model. In: Proceedings of the IEEE ISCAS, Atlanta, vol 4, pp 412–415
Kozlov MK, Tarasov SP, Khachiyan LG (1979) Polynomial solvability of convex quadratic programming. Sov Math Dokl 20:1108–1111
Mo Y-Y, Chu C (2001) A hybrid dynamic/quadratic programming algorithm for interconnect tree optimization. IEEE Trans Comput-Aided Des 20(5):680–686
Sapatnekar SS (1994) RC interconnect optimization under the Elmore delay model. In: Proceedings of the ACM/IEEE design automation conference, San Diego, pp 387–391
Fishburn JP, Schevon CA (1995) Shaping a distributed-RC line to minimize Elmore delay. IEEE Trans Circuits Syst-I Fundam Theory Appl 42(12):1020–1022
Chen C-P, Chen Y-P, Wong DF (1996) Optimal wire-sizing formula under the Elmore delay model. In: Proceedings of the ACM/IEEE design automation conference, Las Vegas, pp 487–490
Cong J, He L (1996) Optimal wiresizing for interconnects with multiple sources. ACM Trans Des Autom Electron Syst 1(4):568–574
Fishburn JP (1997) Shaping a VLSI wire to minimize Elmore delay. In: Proceedings of the European design and test conference, Paris, pp 244–251
Chen C-P, Wong DF (1997) Optimal wire-sizing function with fringing capacitance consideration. In: Proceedings of the ACM/IEEE design automation conference, Anaheim, pp 604–607
Kay R, Bucheuv G, Pileggi L (1997) EWA: efficient wire-sizing algorithm. In: Proceedings of the international symposium on physical design, Napa Valley, pp 178–185
Chu CCN, Wong DF (1999) Greedy wire-sizing is linear time. IEEE Trans Comput-Aided Des 18(4):398–405
Gao Y, Wong DF (2000) Wire-sizing for delay minimization and ringing control using transmission line model. In: Proceedings of the conference on design automation and test in Europe, Paris, pp 512–516
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Chu, C. (2016). Wire Sizing. In: Kao, MY. (eds) Encyclopedia of Algorithms. Springer, New York, NY. https://doi.org/10.1007/978-1-4939-2864-4_483
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DOI: https://doi.org/10.1007/978-1-4939-2864-4_483
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