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Analyzing Cache Behaviour in Multicore Architectures

  • Reference work entry
  • First Online:
Encyclopedia of Algorithms

  • 313 Accesses

Years and Authors of Summarized Original Work

  • 2010; Hassidim

  • 2012; López-Ortiz, Salinger

Problem Definition

Multicore processors are commonly equipped with one or more levels of cache memory, some of which are shared among two or more cores. Multiple cores compete for the use of shared caches for fast access to their program’s data, with the cache usage patterns of a program running on one core, possibly affecting the cache performance of programs running on other cores.

Paging

The management of data across the various levels of the memory hierarchy of modern computers is abstracted by the paging problem. Paging models a two-level memory system with a small and fast memory – known as cache – and a large and slow memory. Data is transferred between the two levels of memory in units known as pages. The input to the problem is a sequence of page requests that must be made available in cache as they are requested. If the currently requested page is already present in the cache, then this...

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Recommended Reading

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Author information

Authors and Affiliations

  1. David R. Cheriton School of Computer Science, University of Waterloo, Waterloo, ON, Canada

    Alejandro López-Ortiz

  2. Department of Computer Science, Saarland University, Saarbücken, Germany

    Alejandro Salinger

Authors
  1. Alejandro López-Ortiz
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  2. Alejandro Salinger
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Corresponding author

Correspondence to Alejandro López-Ortiz .

Editor information

Editors and Affiliations

  1. Department of Electrical Engineering and Computer Science, Northwestern University, Evanston, IL, USA

    Ming-Yang Kao

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López-Ortiz, A., Salinger, A. (2016). Analyzing Cache Behaviour in Multicore Architectures. In: Kao, MY. (eds) Encyclopedia of Algorithms. Springer, New York, NY. https://doi.org/10.1007/978-1-4939-2864-4_534

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