Abstract
Verification of cyber-physical systems SW often requires simulation of accurate heterogeneous HW models. However, heterogeneous system simulators do not easily allow it and designers must connect multiple simulators in complex co-simulation environments. Furthermore, usually HW computing platforms are “approximated” by using abstracted models that do not accurately reproduce the cycle-based execution of HW components. In this chapter we present the automatic generation of cycle-accurate Simulink blocks from the most popular HW description languages: VHDL and Verilog.
The methodology starts from an IP core modeled in one of the two supported HW description languages. Then, it relies on state-of-the-art RTL models abstraction method to generate a functionally equivalent cycle-accurate model of the IP. Then, it uses two alternative mapping and code-generation techniques. The first relying on the portable FMI standard, while the other one exploits Mathworks’ proprietary C MEX S-Functions. These blocks can be easily integrated within Simulink to simulate digital HW components while avoiding to build complex co-simulation environments. A set of IP cores are used to evaluate the proposed approach. Furthermore, the experiments presented in this chapter compares the two proposed mapping and code-generation alternatives to highlight their advantages and drawbacks.
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Notes
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Names of input and output parameters of the output function are fixed by Simulink. Inputs are named uN and outputs are named yM, where N and M are Natural numbers. Output variables must be arrays, being them passed by reference to the output function.
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Centomo, S., Lora, M., Portaluri, A., Stefanni, F., Fummi, F. (2019). Automatic Integration of HDL IPs in Simulink Using FMI and S-Function Interfaces. In: Große, D., Vinco, S., Patel, H. (eds) Languages, Design Methods, and Tools for Electronic System Design. Lecture Notes in Electrical Engineering, vol 530. Springer, Cham. https://doi.org/10.1007/978-3-030-02215-0_1
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