Abstract
The systems with emerging technologies like Internet-of-Things and beyond Von-Neumann architectures can be produced in large scale only if they are resilient-aware, cost-effective and secure. The resilient and cost-effective solutions can be achieved by incorporating fault tolerance techniques at the architecture level of the system design is one of the plausible solutions. The choice of various fault tolerance techniques gives the designers a freedom to incorporate these in the early stage of the design and in turn leading to high yield and reliable architectures. Through-silicon-via (TSV) interconnects based three-dimensional integrated circuits are emerging technologies consisting of vertical communication between the stacked dies, leading to the decrease of wire length and thus enhances the system performance. However, yield and reliability are the major issues that hinder resilient and cost-effective solutions for 3D-IC design. These can be addressed by incorporation of fault tolerance techniques.
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References
Banerjee, K., Souri, S.J., Kapur, P., Saraswat, K.C.: 3-D ICs: a novel chip design for improving deep-submicrometer interconnect performance and systems-on-chip integration. Proc. IEEE 89(5), 602–633 (2001)
Liu, C.C., Ganusov, I., Burtscher, M., Tiwari, S.: Bridging the processor-memory performance gap with 3D IC technology. IEEE Des. Test Comput. 22(6), 556–564 (2005)
Frank, T., Chappaz, C., Leduc, P., Arnaud, L., Moreau, S., Thuaire, A., El Farhane, R., Anghel, L.: Reliability approach of high density through silicon via (TSV). In: 2010 12th Electronics Packaging Technology Conference (EPTC), December 2010, pp. 321–324. IEEE (2010)
Zhao, Y.: Investigation into Yield and Reliability Enhancement of TSV-Based Three-Dimensional Integration Circuits. Doctoral Dissertation, University of Southampton (2014)
Athikulwongse, K., Yang, J.S., Pan, D.Z., Lim, S.K.: Impact of mechanical stress on the full chip timing for through-silicon-via-based 3-D ICs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(6), 905–917 (2013)
Liu, X., Chen, Q., Dixit, P., Chatterjee, R., Tummala, R.R., Sitaraman, S.K.: Failure mechanisms and optimum design for electroplated copper through-silicon vias (TSV). In: 59th Electronic Components and Technology Conference, 2009. ECTC 2009, pp. 624–629. IEEE (2009)
Jung, M., Mitra, J., Pan, D.Z., Lim, S.K.: TSV stress-aware full-chip mechanical reliability analysis and optimization for 3D IC. Commun. ACM 57(1), 107–115 (2014)
Lu, K.H., Zhang, X., Ryu, S.K., Im, J., Huang, R. Ho, P.S.: Thermo-mechanical reliability of 3-D ICs containing through silicon vias. In: 59th Proceedings of Electronic Components and Technology Conference. ECTC 2009, pp. 630–634. IEEE (2009)
Lu, K.H., Ryu, S.K., Zhao, Q., Zhang, X., Im, J., Huang, R., Ho, P.S.: Thermal stress induced delamination of through silicon vias in 3-D interconnects. In: 2010 Proceedings of 60th Electronic Components and Technology Conference (ECTC), pp. 40–45. IEEE (2010)
Ryu, S.K., Lu, K.H., Zhang, X., Im, J.H., Ho, P.S., Huang, R.: Impact of near-surface thermal stresses on interfacial reliability of through-silicon vias for 3-D interconnects. IEEE Trans. Device Mater. Reliab. 11(1), 35–43 (2011)
Kao, C.R., Wu, A.T., Tu, K.N., Lai, Y.S.: Reliability of micro-interconnects in 3D IC packages. Microelectron. Reliab. 53(1), 1 (2013)
Ko, C.T., Chen, K.N.: Reliability of key technologies in 3D integration. Microelectron. Reliab. 53(1), 7–16 (2013)
Tu, K.N.: Reliability challenges in 3D IC packaging technology. Microelectron. Reliab. 51(3), 517–523 (2011)
Chakrabarty, K., Deutsch, S., Thapliyal, H., Ye, F.: TSV defects and TSV-induced circuit failures: The third dimension in test and design-for-test. In: 2012 IEEE International Conference on Reliability Physics Symposium (IRPS), pp. 5F–1. IEEE (2012)
Lin, Y.M., Zhan, C.J., Juang, J.Y., Lau, J.H., Chen, T.H., Lo, R., Kao, M., Tian, T., Tu, K.N.: Electromigration in Ni/Sn intermetallic micro bump joint for 3D IC chip stacking. In: 2011 IEEE 61st Electronic Components and Technology Conference (ECTC), pp. 351–357. IEEE (2011)
Frank, T., Moreau, S., Chappaz, C., Leduc, P., Arnaud, L., Thuaire, A., Chery, E., Lorut, F., Anghel, L., Poupon, G.: Reliability of TSV interconnects: electromigration, thermal cycling, and impact on above metal level dielectric. Microelectron. Reliab. 53(1), 17–29 (2013)
Tan, Y.C., Tan, C.M., Zhang, X.W., Chai, T.C., Yu, D.Q.: Electromigration performance of through silicon Via (TSV)—a modeling approach. Microelectron. Reliab. 50(9), 1336–1340 (2010)
Pak, J., Pathak, M., Lim, S.K., Pan, D.Z.: Modeling of electromigration in through-silicon-via based 3D IC. In: 2011 IEEE 61st Proceedings of Electronic Components and Technology Conference (ECTC), pp. 1420–1427. IEEE (2011)
Hsieh, A.C., Hwang, T.: TSV redundancy: architecture and design issues in 3-D IC. IEEE Trans. Very Large Scale Integr. VLSI Syst. 20(4), 711–722 (2012)
Loi, I., Mitra, S., Lee, T.H., Fujita, S. Benini, L.: A low-overhead fault tolerance scheme for TSV-based 3D network on chip links. In: Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design, November 2008, pp. 598–602. IEEE Press (2008)
Jiang, L., Xu, Q., Eklow, B.: On effective TSV repair for 3D-stacked ICs. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), March 2012, pp. 793–798. IEEE (2012)
Kawano, M., Uchiyama, S., Egawa, Y., Takahashi, N., Kurita, Y., Soejima, K., Komuro, M., Matsui, S., Shibata, K., Yamada, J., Ishino, M.: A 3D packaging technology for 4 Gbit stacked DRAM with 3 Gbps data transfer. In: IEDM’06 International on Electron Devices Meeting, 2006, pp. 1–4. IEEE (2006)
Zhang, T., Wang, K., Feng, Y., Song, X., Duan, L., Xie, Y., Cheng, X., Lin, Y.L.: A customized design of DRAM controller for on-chip 3D DRAM stacking. In: 2010 Custom Integrated Circuits Conference (CICC), pp. 1–4. IEEE (2010)
Jiang, L., Ye, F., Xu, Q., Chakrabarty, K., Eklow, B.: May. On effective and efficient in-field TSV repair for stacked 3D ICs. In: 2013 50th ACM/EDAC/IEEE on Design Automation Conference (DAC), pp. 1–6. IEEE (2013)
Zhao, Y., Khursheed, S., Al-Hashimi, B.M.: Online fault tolerance technique for TSV-based 3-D-IC. IEEE Trans. Very Large Scale Integr. VLSI Syst. 23(8), 1567–1571 (2015)
Reddy, R.P., Acharyya, A., Khursheed, S.: A cost-effective fault tolerance technique for functional TSV in 3-D ICs. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. (2017)
Haykin, S.: Communication Systems. Wiley, New York, NY, USA (2008)
Katti, G., Stucchi, M., De Meyer, K., Dehaene, W.: Electrical modeling and characterization of through silicon via for three-dimensional ICs. IEEE Trans. Electron Devices 57(1), 256–262 (2010)
Ye, F., Chakrabarty, K.: TSV open defects in 3D integrated circuits: characterization, test, and optimal spare allocation. In: 2012 Proceedings of the 49th Annual Design Automation Conference, pp. 1024–1030. ACM (2012)
Cho, M., Liu, C., Kim, D.H., Lim, S.K., Mukhopadhyay, S.: Design method and test structure to characterize and repair TSV defect induced signal degradation in 3D system. In: Proceedings of the International Conference on Computer-Aided Design, November 2011, pp. 694–697. IEEE Press (2010)
Sung, H., Cho, K., Yoon, K., Kang, S.: A delay test architecture for TSV with resistive open defects in 3-D stacked memories. IEEE Trans. Very Large Scale Integr. VLSI Syst. 22(11), 2380–2387 (2014)
Lu, T., Serafy, C., Yang, Z., Samal, S., Lim, S.K., Srivastava, A.: TSV-based 3D ICs: design methods and tools. IEEE Trans. Comput.-Aided Design Integr. Circuits Syst. (2017)
Zhao, Y., Khursheed, S., Al-Hashimi, B.M.: Cost-effective TSV grouping for yield improvement of 3D-ICs. In: 2011 20th Asian Test Symposium (ATS), pp. 201–206. IEEE (2011)
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Reddy, R.P., Acharyya, A., Khursheed, S. (2019). Fault Tolerance in 3D-ICs. In: Chakraborty, R., Mathew, J., Vasilakos, A. (eds) Security and Fault Tolerance in Internet of Things. Internet of Things. Springer, Cham. https://doi.org/10.1007/978-3-030-02807-7_8
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DOI: https://doi.org/10.1007/978-3-030-02807-7_8
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