Abstract
A typical echograph transmits ultrasound signals and receives backscattered echoes through several tens of small transducers that compose the array of the probe. The system should process the acquired echoes in a very short time, typically few tens of ms, so that the medical doctor does not perceive any delay between the probe movements and the image update. This implies, especially when high-frame rate is required, the real-time processing of several GB of data per second: a huge constraint that is even emphasized in the new advanced ultrasound modalities investigated nowadays. In this paper, we present a Field Programmable Gate Array architecture which uses a combination of parallel and serial strategies capable to achieve a throughput rate of 3.5 GB/s in ultrasound data processing. The proposed architecture is implemented in the research ultrasound system ULA-OP 256. The performance of this approach is demonstrated by the real-time implementation of Plane Wave Vector Doppler, a novel investigation method that shows the blood velocity fields over a 2D section of an artery. Tests in a carotid artery of a volunteer are presented.
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Acknowledgements
Authors would like to express their deep gratitude to Professor Piero Tortoli, for his guidance in this research work.
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Meacci, V. et al. (2019). FPGA-Based Multi Cycle Parallel Architecture for Real-Time Processing in Ultrasound Applications. In: Saponara, S., De Gloria, A. (eds) Applications in Electronics Pervading Industry, Environment and Society. ApplePies 2018. Lecture Notes in Electrical Engineering, vol 573. Springer, Cham. https://doi.org/10.1007/978-3-030-11973-7_34
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