Abstract
The paper presents an analysis of principal parasitic effects in contactless wafer-level testing. Contactless technology exploits an inductive coupling between a tester antenna and many integrated on-chip antennas (OCAs) able to transfer energy and exchange bidirectional data. Electromagnetic crosstalk between adjacent on-chip antennas and the eddy currents generated in the substrate were analyzed. Simulations, varying the thickness and the conductivity of the substrate, have highlighted the strengths of this approach. Moreover, a wafer scribe line pre-cutting, used to drastically reducing the eddy currents, was also adopted.
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Finocchiaro, A., Girlando, G., Motta, A., Pagani, A., Palmisano, G. (2019). Main Parasitic Effects in Contactless Wafer Testing. In: Saponara, S., De Gloria, A. (eds) Applications in Electronics Pervading Industry, Environment and Society. ApplePies 2018. Lecture Notes in Electrical Engineering, vol 573. Springer, Cham. https://doi.org/10.1007/978-3-030-11973-7_9
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DOI: https://doi.org/10.1007/978-3-030-11973-7_9
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