Skip to main content
SpringerLink
Log in

Design of Low Power SAR ADC with Two Different DAC Structure and Two Different SAR Logic Designs and Their Comparisons

  • Conference paper
  • First Online:
Intelligent Systems Design and Applications (ISDA 2018 2018)

Part of the book series: Advances in Intelligent Systems and Computing ((AISC,volume 940))

Abstract

Successive-approximation analog-to-digital converters (SA-ADCs) are widely used in ultra-low-power applications. In this paper the power consumption and linearity of SAR ADC are analyzed by using different DAC structures and different SAR Logics. Three types of DAC structures i.e. Capacitive DAC, R-2R resistive DAC, and a CMOS R-2R ladder DAC is employed. Coming to SAR logic, sequential/code register and non-redundant SAR logics are used. Among the all, the CMOS R-2R ladder DAC and non-redundant SAR logic structured SA-ADC is efficient and provides optimum results for all circuit design aspects i.e. power, speed, and area. Along above all designs a dynamic two-stage comparator and the D flip-flops with transmission gates are used due to their energy efficiency and capability of working in low supply voltages.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Log in via an institution
Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 169.00
Price excludes VAT (USA)
  • Available as EPUB and PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 219.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

Similar content being viewed by others

References

  1. Wong, L.S., Hossain, S., Ta, A., Edvinsson, J., Rivas, D.H., Naas, H.: A very low-power CMOS mixed-signal IC for implantable pacemaker applications. IEEE J. Solid-State Circuits 39(12), 2446–2456 (2004)

    Article  Google Scholar 

  2. Shahrokhi, F., Abdelhalim, K., Serletis, D., Carlen, P.L., Genov, R.: The 128-channel fully differential digital integrated neural recording and stimulation interface. IEEE Trans. Biomed. Circuits Syst. 4(3), 149–161 (2010)

    Article  Google Scholar 

  3. Kim, S., Lee, S.J., Cho, N.: A fully integrated digital hearing aid chip with human factors considerations. IEEE J. Solid-State Circuits 43(1), 266–274 (2008)

    Article  Google Scholar 

  4. Yangjin, O., Murmann, B.: System embedded ADC calibration for OFDM receivers. IEEE Trans. Circuits Syst. I 53(8), 1693–1703 (2006)

    Article  Google Scholar 

  5. Scott, M.D., Boser, B.E., Pister, K.S.: An ultralow-energy ADC for smart dust. IEEE J. Solid-State Circuits 38(7), 1123–1129 (2003)

    Article  Google Scholar 

  6. Verma, N., Chandrakasan, A.P.: An ultra low energy 12-bit rate-resolution scalable SAR ADC for wireless sensor nodes. IEEE J. Solid-State Circuits 42(6), 1196–1205 (2007)

    Article  Google Scholar 

  7. Gambini, S., Rabaey, J.: Low-power successive approximation converter with 0.5 V supply in 90 nm CMOS. IEEE J. Solid-State Circuits 42(11), 2348–2356 (2007)

    Article  Google Scholar 

  8. Sauerbrey, J., Schmitt-Landsiedel, D., Thewes, R.: A 0.5-V 1-/spl mu/W successive approximation ADC. IEEE J. Solid-State Circuits 38(7), 1261–1265 (2003)

    Google Scholar 

  9. Suarez, E., Gray, P.R., Hodges, D.A.: All-MOS charge redistribution analog-to-digital conversion techniques—Part I. IEEE J. Solid-State Circuits 10(6), 371–379 (1975)

    Article  Google Scholar 

  10. Hong, H., Lee, G.: A 65-fJ/conversion-step 0.9-V 200-kS/s rail-to-rail 8-bit successive approximation ADC. IEEE J. Solid-State Circuits 42(10), 2161–2168 (2007)

    Google Scholar 

  11. Singh, R.R., et al.: Multi-step binary-weighted capacitive digital-toanalog converter architecture. In: Proceedings of IEEE MWSCAS, pp. 470–473, August 2008

    Google Scholar 

  12. Baker, R.J.: CMOS Circuit Design, Layout, and Simulation, 2nd edn. Wiley, New York (2004)

    Google Scholar 

  13. Culurciello, E., Andreou, A.G.: An 8-bit 800-$ muhboxW $1.23-MS/s successive approximation ADC in SOI CMOS. IEEE Trans. Circuits Syst. II: Exp. Briefs 53(9), 858–861 (2006)

    Google Scholar 

  14. Zhu, Y., Chan, C.H., Chio, U.F., Sin, S.W., Seng-Pan, U., Martins, R.P., Maloberti, F.: A 10-bit 100-MS/s reference-free SAR ADC in 90 nm CMOS. IEEE J. Solid-State Circuits 45(6), 1111–1121 (2010)

    Google Scholar 

  15. Zhu, Y., Chio, U., Wei, H., Sin, S., Seng-Pan, U., Martins, R.P.: A power-efficient capacitor structure for high-speed charge recycling SAR ADCs. In: Proceedings of IEEE ICECS, pp. 642–645, September 2008

    Google Scholar 

  16. Ginsburg, B.P., Chandrakasan, A.P.: 500-MS/s 5-bit ADC in 65-nm CMOS with split capacitor array DAC. IEEE J. Solid-State Circuits 42(4), 739–747 (2007)

    Article  Google Scholar 

  17. Ginsburg, B.P., Chandrakasan, A.P.: An energy-efficient charge recycling approach for a SAR converter with capacitive DAC. In: Proceedings of IEEE ISCAS, pp. 184–187, May 2005

    Google Scholar 

  18. Choi, R.Y.-K., Tsui, C.-Y.: A low energy two-step successive approximation algorithm for ADC design. In: Proceedings of IEEE ISQED, pp. 317–320, March 2008

    Google Scholar 

  19. Liew, W.S., et al.: A 1-V 60-μW 16-channel interface chip for implantable neural recording. In: Proceedings of IEEE CICC, pp. 507–510, September 2009

    Google Scholar 

  20. Cong, L.: Pseudo C-2C ladder-based data converter technique. IEEE Trans. Circuits Syst. II 48(10), 927–929 (2001)

    Google Scholar 

  21. Lee, S.-W., Chung, H.-J., Han, C.-H.: C-2C digital-to-analogue converter on insulator. Electron. Lett. 35(15), 1242–1243 (1999)

    Article  Google Scholar 

  22. Kim, H., Min, Y., Kim, Y., Kim, S.: A low power consumption 10-bit rail-to-rail SAR ADC using a C-2C capacitor array. In: Proceedings of IEEE EDSSC, pp. 1–4, December 2008

    Google Scholar 

  23. Xiong, W., Yang, G., Murmann, B., Zschieschang, U., Klauk, H.: A3-V, 6-bit C-2C digital-to-analog converter using complementary organic thin-film transistors on glass. In: Proceedings of IEEE ESSDERC, pp. 229–232, September 2009

    Google Scholar 

  24. Lee, J.S., Park, I.C.: Capacitor array structure and switch control for energy-efficient SAR analog-to-digital converters. In: Proceedings of IEEE ISCAS, pp. 236–239, May 2008

    Google Scholar 

  25. Zhu, Y., et al.: Linearity analysis on a series-split capacitor array for high-speed SAR ADCs. In: Proceedings of IEEE MWSCAS, pp. 922–925, August 2008

    Google Scholar 

  26. Kuttner, F.: A 1.2 V 10b 20 MSample/s non-binary successive approximation ADC in 0.13 μm CMOS. In: Proceedings of IEEE ISSCC, pp. 176–177 (2002)

    Google Scholar 

  27. Gan, J., Abraham, J.: Mixed-signal micro-controller for non-binary capacitor array calibration in data converter. In: Proceeding of IEEE Signals, Systems and Computers Conference, vol. 2, pp. 1046–1049, November 2002

    Google Scholar 

  28. Gan, J., Abraham, J.: A non-binary capacitor array calibration circuit with 22-bit accuracy in successive approximation analog-to-digital converters. In: Proceedings of IEEE MWSCAS, vol. 1, pp. 301–304, August 2002

    Google Scholar 

  29. Suarez, R.E., Gray, P.R., Hodges, D.A.: All-MOS charge-redistribution analog-to-digital conversion techniques—Part II. IEEE J. Solid-State Circuits SC-10(6), 379–385 (1975)

    Article  Google Scholar 

  30. Craninckx, J., Plas, G.V.: A 65fJ/conversion-step 0-to-50 MS/s 0-to-0.7 mW 9b charge-sharing SAR ADC in 90 nm digital CMOS. In: Proceedings of IEEE ISSCC Digest of Technical Papers, pp. 246–600, February 2007

    Google Scholar 

  31. Le, H.P., Singh, J., Hiremath, L., Mallapur, V., Stojcevski, A.: Ultra-low-power variable-resolution successive approximation ADC for biomedical application. Electron. Lett. 41(11), 634–635 (2005)

    Article  Google Scholar 

  32. Robert, P.Y., Gosselin, B., Ayoub, A.E., Sawan, M.: An ultra-low-power successive-approximation-based ADC for implantable sensing devices. In: Proceedings of IEEE MWSCAS, vol. 1, pp. 7–11, August 2006

    Google Scholar 

  33. Saul, P.H.: Successive approximation analog-to-digital conversion at video rates. IEEE J. Solid-State Circuits sc-16(3), 147–151 (1981)

    Article  Google Scholar 

  34. Yang, Z., der Spiegel, J.V.: A 10-bit 8.3 MS/s switch-current successive approximation ADC for column-parallel imagers. In: Proceedings of IEEE ISCAS, pp. 224–227, May 2008

    Google Scholar 

  35. Dlugosz, R., Iniewski, K.: Ultra low power current-mode algorithmic analog-to-digital converter implemented in 0.18 μm CMOS technology for wireless sensor network. In: Proceedings of IEEE MIXDES, pp. 401–406, June 2006

    Google Scholar 

  36. Mortezapour, S., Lee, E.K.: A 1-V, 8-bit successive approximation ADC in standard CMOS process. IEEE J. Solid-State Circuits 35(4), 642–646 (2000)

    Article  Google Scholar 

  37. Hammerschmied, C.M., Huang, Q.: Design and implementation of an untrimmed MOSFET-only 10-bit A/D converter with 79-dB THD. IEEE J. Solid-State Circuits 33(8), 1148–1157 (1998)

    Article  Google Scholar 

  38. Lin, C.S., Liu, B.D.: A new successive approximation architecture for low-power low-cost CMOS A/D converter. IEEE J. Solid-State Circuits 38(1), 54–62 (2003)

    Article  Google Scholar 

  39. Fayomi, C.J.B., Roberts, G.W., Sawan, M.: A 1-V, 10-bit rail-torail successive approximation analog-to-digital converter in standard 0.18 μm CMOS technology. In: Proceedings of IEEE ISCAS, pp. 460–463, May 2001

    Google Scholar 

  40. Shyu, J.B., Temes, G.C., Yao, K.: Random errors in MOS capacitors. IEEE J. Solid-State Circuits 17(6), 1070–1076 (1982)

    Article  Google Scholar 

  41. Fayomi, C.J.-B., Roberts, G.W., Sawan, M.: Low-voltage CMOS analog switch for high precision sample-and-hold circuit. In: 43rd Midwest Symposium on Circuits and Systems, East Lansing, August 2000

    Google Scholar 

  42. Samavati, H., et al.: Fractal capacitors. IEEE J. Solid-State Circuits 33(12), 2035–2041 (1998)

    Article  Google Scholar 

  43. Kazeminia, S., Hesamiafshar, Y., Hadidi, K., Khoei, A.: On matching properties of R-2R ladders in high performance digital-to-analog converters. In: 2010 18th Iranian Conference on Electrical Engineering (ICEE), pp. 432–436, May 2010

    Google Scholar 

Download references

Author information

Authors and Affiliations

  1. Potti Sri Ramulu Chalavadi Mallikarjuna Rao College of Engineering and Technology, Vijayawada, AP, India

    Aruna Kumari Chirapangi, G. M. G. Madhuri, Praveen Kitti Burri & Naga Lakshmi Kalyani Movva

Authors
  1. Aruna Kumari Chirapangi
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. G. M. G. Madhuri
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Praveen Kitti Burri
    View author publications

    You can also search for this author in PubMed Google Scholar

  4. Naga Lakshmi Kalyani Movva
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding authors

Correspondence to Aruna Kumari Chirapangi or Naga Lakshmi Kalyani Movva .

Editor information

Editors and Affiliations

  1. Machine Intelligence Research Labs, Auburn, WA, USA

    Ajith Abraham

  2. School of Information Technology and Engineering, Vellore Institute of Technology, Vellore, Tamil Nadu, India

    Aswani Kumar Cherukuri

  3. Tijuana Institute of Technology, Tijuana, Mexico

    Patricia Melin

  4. Machine Intelligence Research Labs, Auburn, WA, USA

    Niketa Gandhi

Rights and permissions

Reprints and permissions

Copyright information

© 2020 Springer Nature Switzerland AG

About this paper

Check for updates. Verify currency and authenticity via CrossMark

Cite this paper

Chirapangi, A.K., Madhuri, G.M.G., Burri, P.K., Movva, N.L.K. (2020). Design of Low Power SAR ADC with Two Different DAC Structure and Two Different SAR Logic Designs and Their Comparisons. In: Abraham, A., Cherukuri, A.K., Melin, P., Gandhi, N. (eds) Intelligent Systems Design and Applications. ISDA 2018 2018. Advances in Intelligent Systems and Computing, vol 940. Springer, Cham. https://doi.org/10.1007/978-3-030-16657-1_81

Download citation

Publish with us

Policies and ethics

Search

Navigation