Abstract
Mixed-criticality systems integrate tasks with various levels of criticality onto the same hardware platform. Critical tasks require tight bounding of worst case latency at any cost, yet for non-critical tasks it is important to provide high performance as much as possible. In this paper, we take workload-driven approach and propose a novel workload-aware DRAM controller design for mixed-criticality system that can successfully achieve both of the conflicting demands in the presence of memory-intensive workloads. By using bank partitioning and request batching with prioritization, we provide tighter worst case latency bound for critical tasks and high performance and fairness for non-critical tasks. Our evaluation shows that the design achieves maximum 18% of performance improvement.
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Acknowledgement
This research was partly supported by the MSIT (Ministry of Science and ICT), Korea, under the SW Starlab (IITP-2015-0-00209) supervised by the IITP (Institute for Information & Communications Technology Promotion) and partly supported by Next-Generation Information Computing Development Program through the National Research Foundation of Korea (NRF) funded by the MSIT (2017M3C4A7065925, On-the-fly Machine Learning and Its Specialized Real-time/Security System SW for Evolving Intelligent CPS).
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Eo, J., Kim, KW., Lee, CG. (2019). Memory Access Pattern-Aware DRAM Controller Design for Mixed-Criticality Systems. In: Chamberlain, R., Taha, W., Törngren, M. (eds) Cyber Physical Systems. Design, Modeling, and Evaluation. CyPhy 2017. Lecture Notes in Computer Science(), vol 11267. Springer, Cham. https://doi.org/10.1007/978-3-030-17910-6_3
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