Abstract
Off-the-shelf multi-core processors provide a cost-efficient alternative to expensive special purpose processors at the cost of complex time predictability due to shared resources like buses, caches and the memory itself. This paper presents an operating system concept that takes control over the shared cache to minimize contention, by creating a component-based operating system, that is structured in small data chunks to allow better control over data and code movement in and out of the cache. An evaluation of the operating system shows that the system is able to reduce the difference between the ACET and observed WCET of a synthetic memory load test by 93% for ARM and 98% for Intel systems. Some noteworthy improvements were also achieved for the TACLe benchmarks.
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Notes
- 1.
Evaluated on an Intel Xeon E5-1620 v4 processor with 20 cache ways.
- 2.
Verified on NXP i.MX6 and Samsung Exynos 4412.
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The source code of the prototype implementation is available under: https://github.com/ESS-Group/CyPhOS.
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Borghorst, H., Spinczyk, O. (2019). CyPhOS – A Component-Based Cache-Aware Multi-core Operating System. In: Schoeberl, M., Hochberger, C., Uhrig, S., Brehm, J., Pionteck, T. (eds) Architecture of Computing Systems – ARCS 2019. ARCS 2019. Lecture Notes in Computer Science(), vol 11479. Springer, Cham. https://doi.org/10.1007/978-3-030-18656-2_13
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