Abstract
Convolutional Neural Networks (CNNs) require highly parallel Hardware (HW) accelerators in the form of Graphical Processing Units (GPUs), Application Specific Integrated Circuits (ASICs) or Field Programmable Gate Arrays (FPGAs) to build low latency solutions necessary for implementing image processing applications. FPGAs have the ability to provide a right balance between flexibility, performance and energy efficiency. The design of FPGA based accelerator design traditionally required a tedious Register Transfer Level (RTL) design flow process. To improve design productivity, the proposed work uses High-Level Synthesis (HLS), described in OpenCL, to generate the FPGA bitstream for the CNN model. The 2D Winograd transformation is integrated in the pipeline to reduce the overall number of Multiply and Accumulate (MAC) operations in the CNN. Instead of increasing the batch size to improve the throughput, this work discusses a mixed precision approach which can counter the limited memory bandwidth issue within the CNN. The obtained results are competitive against other FPGA based implementations proposed in literature. The proposed accelerator can achieve more than \(1.9 \times \) higher energy efficiency compared to an embedded Nvidia Jetson TX1 implementation of VGG-16.
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Notes
- 1.
Each M20K block of Arria 10 consists of 3 read ports and 1 write port. Double pumping is possible with 2 \(\times \) clock frequency.
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Vemparala, M.R., Frickenstein, A., Stechele, W. (2019). An Efficient FPGA Accelerator Design for Optimized CNNs Using OpenCL. In: Schoeberl, M., Hochberger, C., Uhrig, S., Brehm, J., Pionteck, T. (eds) Architecture of Computing Systems – ARCS 2019. ARCS 2019. Lecture Notes in Computer Science(), vol 11479. Springer, Cham. https://doi.org/10.1007/978-3-030-18656-2_18
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