Abstract
Key capabilities of the fifth generation (5G) of cellular mobile communication systems are increased peak and network data rates and an energy efficient operation. Signal processing plays an important role to meet these goals. Recently, it has been shown that, for the problem of vector equalization, signal processing with analog electronic circuits has a large potential for a high-speed and low-power operation. In this paper we consider the problem of decoding for convolutional self-orthogonal codes. We report on a student project where we used standard off-the-shelf electronic components to realize an analog decoder circuit. The starting point is an iterative threshold decoder. Its structure corresponds to the one of a high-order recurrent neural network (HORNN). Structure as well as weights of the HORNN are given directly by the problem. The dynamics of the HORNN can be implemented in discrete-time, this corresponds to the iterative threshold decoder, or in continuous-time. Both implementations lead to the same asymptotic state, which represents the desired decoder output. The dynamical evolution of the continuous-time HORNN is governed by a system of coupled first-order nonlinear differential equations. Based on that, we design an analog electronic circuit, which solves this set of differential equations. Thus the analog circuit shows a similar dynamical behavior as the continuous-time HORNN, and especially also the same asymptotic state.
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Notes
- 1.
Note, the term analog is used here in a twofold meaning. First, it indicates an electronic circuit which matches with the original mathematical problem, and second, it characterizes a circuit for continuous-time and continuous-range signals.
- 2.
Actually it turns out, that this code is also a CSO\(^2\)C.
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Acknowledgment
The authors would like to thank Mohamad Mostafa and Jürgen Lindner for many valuable discussions on the topic of signal processing with RNN. We thank Hermann Schumacher and Andreas Trasser for sharing their expertise in the design of analog circuits.
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Teich, W.G., Teich, H., Oliveri, G. (2019). From Iterative Threshold Decoding to a Low-Power High-Speed Analog VLSI Decoder Implementation. In: Rojas, I., Joya, G., Catala, A. (eds) Advances in Computational Intelligence. IWANN 2019. Lecture Notes in Computer Science(), vol 11507. Springer, Cham. https://doi.org/10.1007/978-3-030-20518-8_51
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