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Transaction Protocol Verification with Labeled Synchronization Logic

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NASA Formal Methods (NFM 2019)

Part of the book series: Lecture Notes in Computer Science ((LNPSE,volume 11460))

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Abstract

Synchronization algorithms that provide the transaction interface are intricate. We present an algorithm description language that explicitly captures the type of the used synchronization objects and associates labels to method calls to explicitly capture their intra-thread order. We use the language to capture architecture independent representations of transactional memory (TM) algorithms. We present a novel logic that enables reasoning about synchronization algorithms that are described in the language. The logic quantifies over program labels and provides specific predicates and intuitive inference rules to reason about the inter-thread execution and linearization orders of labeled method calls. In particular, the logic assertions can directly capture orders that are fundamental to the correctness of transactions. We present a denotational semantics for the language and prove the soundness of the logic. We have formalized the logic in the PVS proof assistant and mechanically constructed the challenging correctness proof of the TL2 TM algorithm.

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References

  1. Armstrong, A., Dongol, B., Doherty, S.: Proving opacity via linearizability: a sound and complete method. In: Bouajjani, A., Silva, A. (eds.) FORTE 2017. LNCS, vol. 10321, pp. 50–66. Springer, Cham (2017). https://doi.org/10.1007/978-3-319-60225-7_4

    Chapter  Google Scholar 

  2. Attiya, H., Gotsman, A., Hans, S., Rinetzky, N.: A programming language perspective on transactional memory consistency. In: Proceedings of the 2013 ACM Symposium on Principles of Distributed Computing, PODC 2013, pp. 309–318. ACM, New York (2013)

    Google Scholar 

  3. Baek, W., Bronson, N., Kozyrakis, C., Olukotun, K.: Implementing and evaluating a model checker for transactional memory systems. In: 2010 15th IEEE International Conference on Engineering of Complex Computer Systems (ICECCS), pp. 117–126 (2010)

    Google Scholar 

  4. Bender, J., Lesani, M., Palsberg, J.: Declarative fence insertion. In: OOPSLA 2015, pp. 367–385 (2015)

    Article  Google Scholar 

  5. Cohen, A., O’Leary, J.W., Pnueli, A., Tuttle, M.R., Zuck, L.D.: Verifying correctness of transactional memories. In: FMCAD (2007)

    Google Scholar 

  6. Cohen, A., Pnueli, A., Zuck, L.D.: Mechanical verification of transactional memories with non-transactional memory accesses. In: Gupta, A., Malik, S. (eds.) CAV 2008. LNCS, vol. 5123, pp. 121–134. Springer, Heidelberg (2008). https://doi.org/10.1007/978-3-540-70545-1_13

    Chapter  MATH  Google Scholar 

  7. Dalessandro, L., Spear, M.F., Scott, M.L.: NOrec: streamlining STM by abolishing ownership records. In: PPoPP (2010)

    Google Scholar 

  8. Derrick, J., Dongol, B., Schellhorn, G., Travkin, O., Wehrheim, H.: Verifying opacity of a transactional mutex lock. In: Bjørner, N., de Boer, F. (eds.) FM 2015. LNCS, vol. 9109, pp. 161–177. Springer, Cham (2015). https://doi.org/10.1007/978-3-319-19249-9_11

    Chapter  Google Scholar 

  9. Dice, D., Shalev, O., Shavit, N.: Transactional locking II. In: Dolev, S. (ed.) DISC 2006. LNCS, vol. 4167, pp. 194–208. Springer, Heidelberg (2006). https://doi.org/10.1007/11864219_14

    Chapter  Google Scholar 

  10. Dijkstra, E.W.: Cooperating sequential processes, technical report EWD-123 (1965)

    Google Scholar 

  11. Doherty, S., Dongol, B., Derrick, J., Schellhorn, G., Wehrheim, H.: Proving opacity of a pessimistic STM. Leibniz International Proceedings in Informatics, vol. 70, pp. 35:1–35:17. Dagstuhl Publishing (2017)

    Google Scholar 

  12. Emmi, M., Majumdar, R., Manevich, R.: Parameterized verification of transactional memories. In: PLDI (2010)

    Article  Google Scholar 

  13. Feng, X.: Local rely-guarantee reasoning. In: POPL 2009 (2009)

    Article  Google Scholar 

  14. Guerraoui, R., Kapalka, M.: On the correctness of transactional memory. In: PPOPP (2008)

    Google Scholar 

  15. Guerraoui, R., Henzinger, T.A., Jobstmann, B., Singh, V.: Model checking transactional memories. In: ACM SIGPLAN Conference on Programming Languages Design and Implementation, pp. 372–382 (2008)

    Article  Google Scholar 

  16. Guerraoui, R., Henzinger, T.A., Singh, V.: Software transactional memory on relaxed memory models. In: Bouajjani, A., Maler, O. (eds.) CAV 2009. LNCS, vol. 5643, pp. 321–336. Springer, Heidelberg (2009). https://doi.org/10.1007/978-3-642-02658-4_26

    Chapter  Google Scholar 

  17. Guerraoui, R., Henzinger, T.A., Singh, V.: Model checking transactional memories. Distrib. Comput. 22, 129–145 (2010)

    Article  Google Scholar 

  18. Hawblitzel, C., Petrank, E., Qadeer, S., Tasiran, S.: Automated and modular refinement reasoning for concurrent programs. In: Kroening, D., Păsăreanu, C.S. (eds.) CAV 2015, Part II. LNCS, vol. 9207, pp. 449–465. Springer, Cham (2015). https://doi.org/10.1007/978-3-319-21668-3_26

    Chapter  Google Scholar 

  19. Herlihy, M.P., Wing, J.M.: Linearizability: a correctness condition for concurrent objects. TOPLAS 12(3), 463–492 (1990)

    Article  Google Scholar 

  20. Hobor, A., Appel, A.W., Nardelli, F.Z.: Oracle semantics for concurrent separation logic. In: Drossopoulou, S. (ed.) ESOP 2008. LNCS, vol. 4960, pp. 353–367. Springer, Heidelberg (2008). https://doi.org/10.1007/978-3-540-78739-6_27

    Chapter  Google Scholar 

  21. Jones, C.B.: Specification and design of (parallel) programs. In: Information Processing 83, vol. 9, pp. 321–332 (1983)

    Google Scholar 

  22. Jung, R., Krebbers, R., Birkedal, L., Dreyer, D.: Higher-order ghost state. In: Proceedings of the 21st ACM SIGPLAN International Conference on Functional Programming, ICFP 2016, pp. 256–269. ACM, New York (2016)

    Google Scholar 

  23. Jung, R., et al.: Iris: monoids and invariants as an orthogonal basis for concurrent reasoning. In: POPL 2015 (2015)

    Article  Google Scholar 

  24. Khyzha, A., Attiya, H., Gotsman, A., Rinetzky, N.: Safe privatization in transactional memory. In: Proceedings of the 23rd ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, pp. 233–245. ACM (2018)

    Google Scholar 

  25. Lamport, L.: On interprocess communication. Part I: basic formalism. Distrib. Comput. 1(2), 77–85 (1986)

    Article  MathSciNet  Google Scholar 

  26. Lesani, M.: PVS Proof Theories (2018). http://www.cs.ucr.edu/%7Elesani/companion/nfm19/PVSTheories.tar.gz

  27. Lesani, M.: Submission appendix (2018). http://www.cs.ucr.edu/%7Elesani/companion/nfm19/Appendix.pdf

  28. Lesani, M., Luchangco, V., Moir, M.: A framework for formally verifying software transactional memory algorithms. In: Koutny, M., Ulidowski, I. (eds.) CONCUR 2012. LNCS, vol. 7454, pp. 516–530. Springer, Heidelberg (2012). https://doi.org/10.1007/978-3-642-32940-1_36

    Chapter  Google Scholar 

  29. Lesani, M., Palsberg, J.: Proving non-opacity. In: Afek, Y. (ed.) DISC 2013. LNCS, vol. 8205, pp. 106–120. Springer, Heidelberg (2013). https://doi.org/10.1007/978-3-642-41527-2_8

    Chapter  Google Scholar 

  30. Lesani, M., Palsberg, J.: Decomposing opacity. In: Kuhn, F. (ed.) DISC 2014. LNCS, vol. 8784, pp. 391–405. Springer, Heidelberg (2014). https://doi.org/10.1007/978-3-662-45174-8_27

    Chapter  Google Scholar 

  31. Liang, H., Feng, X.: Modular verification of linearizability with non-fixed linearization points. In: PLDI 2013, pp. 459–470 (2013)

    Article  Google Scholar 

  32. Lourenço, J., Cunha, G.: Testing patterns for software transactional memory engines. In: Proceedings of the 2007 ACM Workshop on Parallel and Distributed Systems: Testing and Debugging, PADTAD 2007, pp. 36–42. ACM, New York (2007)

    Google Scholar 

  33. Lynch, N., Vaandrager, F.: Forward and backward simulations for timing-based systems. In: de Bakker, J.W., Huizing, C., de Roever, W.P., Rozenberg, G. (eds.) REX 1991. LNCS, vol. 600, pp. 397–446. Springer, Heidelberg (1992). https://doi.org/10.1007/BFb0032002

    Chapter  Google Scholar 

  34. Lynch, N.A., Tuttle, M.R.: An introduction to input/output automata. CWI Q. 2, 219–246 (1989)

    MathSciNet  MATH  Google Scholar 

  35. Manovit, C., Hangal, S., Chafi, H., McDonald, A., Kozyrakis, C., Olukotun, K.: Testing implementations of transactional memory. In: Proceedings of the 15th International Conference on Parallel Architectures and Compilation Techniques, PACT 2006, pp. 134–143. ACM, New York (2006)

    Google Scholar 

  36. Matveev, A., Shavit, N.: Towards a fully pessimistic STM model (2012)

    Google Scholar 

  37. Nanevski, A., Ley-Wild, R., Sergey, I., Delbianco, G.A.: Communicating state transition systems for fine-grained concurrent resources. In: Shao, Z. (ed.) ESOP 2014. LNCS, vol. 8410, pp. 290–310. Springer, Heidelberg (2014). https://doi.org/10.1007/978-3-642-54833-8_16

    Chapter  MATH  Google Scholar 

  38. O’Hearn, P.W.: Resources, concurrency, and local reasoning. Theor. Comput. Sci. 375(1–3), 271–307 (2007)

    Article  MathSciNet  Google Scholar 

  39. O’Leary, J., Saha, B., Tuttle, M.R.: Model checking transactional memory with spin. In: 29th IEEE International Conference on Distributed Computing Systems, ICDCS 2009, pp. 335–342 (2009)

    Google Scholar 

  40. Singh, V.: Runtime verification for software transactional memories. In: Barringer, H., et al. (eds.) RV 2010. LNCS, vol. 6418, pp. 421–435. Springer, Heidelberg (2010). https://doi.org/10.1007/978-3-642-16612-9_32

    Chapter  Google Scholar 

  41. Turon, A., Vafeiadis, V., Dreyer, D.: GPS: navigating weak memory with ghosts, protocols, and separation. In: Proceedings of the 2014 ACM International Conference on Object Oriented Programming Systems Languages & Applications, OOPSLA 2014, pp. 691–707. ACM, New York (2014)

    Google Scholar 

  42. Vafeiadis, V., Parkinson, M.: A marriage of rely/guarantee and separation logic. In: Caires, L., Vasconcelos, V.T. (eds.) CONCUR 2007. LNCS, vol. 4703, pp. 256–271. Springer, Heidelberg (2007). https://doi.org/10.1007/978-3-540-74407-8_18

    Chapter  Google Scholar 

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Authors and Affiliations

  1. University of California, Riverside, USA

    Mohsen Lesani

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  1. Mohsen Lesani
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Correspondence to Mohsen Lesani .

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Editors and Affiliations

  1. NASA, Houston, TX, USA

    Julia M. Badger

  2. Iowa State University, Ames, IA, USA

    Kristin Yvonne Rozier

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Lesani, M. (2019). Transaction Protocol Verification with Labeled Synchronization Logic. In: Badger, J., Rozier, K. (eds) NASA Formal Methods. NFM 2019. Lecture Notes in Computer Science(), vol 11460. Springer, Cham. https://doi.org/10.1007/978-3-030-20652-9_19

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  • DOI: https://doi.org/10.1007/978-3-030-20652-9_19

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